# US 8,543,735 B2 · Semiconductor device and data processing system having reduced number of terminals allocated for externally accessed address > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,543,735 B2 - Document ID: US8543735B2 - Status: Granted - Kind: B2 - Application number: 13/618,369 - Filed: 2012-09-14 - Published: 2013-03-21 - Granted: 2013-09-24 - Earliest claimed: 2010-02-24 - Assignees: Renesas Electronics Corporation - Applicants: Masaaki Hirano; Kunihiko Nishiyama - Inventors: Masaaki Hirano; Kunihiko Nishiyama - Web page: https://patentgrep.com/patent/US8543735B2 ## CPC - G06F 13/385: {for adaptation of a particular data processing system to different peripheral devices} - G06F 12/02: Addressing or allocation; Relocation (program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract There is provided a semiconductor device having a reduced number of external terminals allocated for address input to receive access from outside, while realizing a high-speed response to an access from outside. The semiconductor device employs, in order to allow other external devices to directly access resources it possesses in its own address space, in an external interface circuit, external terminals which input a part of the address signal required for access from outside, a supplementary register which supplements the upper portion of address information that has been input from the external terminals, a mode register accessible from outside, and an address control circuit which generates an address signal to access the address space in a form based on information input from the external terminals, required supplementary information, and mode information of the mode register. ## Claims ### Claim 1 A data processing system comprising: a first data processor; a memory device provided in a part of an address space of the first data processor and coupled to an outside of the first data processor; and a second data processor coupled to an outside of the first data processor, wherein the first data processor includes: a first external interface circuit which controls access to the address space of the first data processor from the second data processor; and a second external interface circuit which controls access to the memory device, wherein the first external interface circuit includes: an external terminal arrangement for inputting, from the second data processor, a part of an address signal used to access the address space; a supplementary register in which supplementary information for supplementing an upper portion of an address information that has been input from the external terminal arrangement is written by the second data processor; a mode register in which mode information is written by the second data processor; and an address control circuit which generates an address signal to access the address space of the first data processor in a form based on information input from the external terminal arrangement, the supplementary register, and the mode register, and wherein the second data processor, after setting the mode register and the supplementary register, outputs address information to the external terminal to issue read access or write access. ### Claim 2 (depends on 1) The data processing system according to claim 1, wherein the form of the address signal generated by the address control circuit includes a first generation form which supplements the address information input from the external terminal arrangement with the supplementary information of the supplementary register. ### Claim 3 (depends on 2) The data processing system according to claim 2, wherein the external terminal arrangement includes an external multiplex terminal and an address input terminal used for address input or data input/output in a switching manner, and inputs, in the first generation form, address information using both the address input terminal and the external multiplex terminal. ### Claim 4 (depends on 1) The data processing system according to claim 1, wherein the form of the address signal generated by the address control circuit includes a second generation form in which, when particular bits of the address information input from the external terminal arrangement are a first value, the address information from the external terminal arrangement excluding the particular bits is defined as a lower portion and the upper portion is defined as a default value assigned to an address of a particular resource, and a third generation form in which, when particular bits of the address information input from the external terminal arrangement are a second value, a predetermined bit string of the address information from the external terminal arrangement is defined as the lower portion and the upper portion is defined as a default value assigned to an address of a resource corresponding to a value of another particular bit array of the information input from the external terminal arrangement. ### Claim 5 (depends on 4) The data processing system according to claim 4, wherein the particular resource is the memory device, and the resource corresponding to the value of the particular bit array is a group of registers built in the first data processor. ### Claim 6 (depends on 4) The data processing system according to claim 4, wherein: the external terminal arrangement includes an external multiplex terminal and an address input terminal used for address input or data input/output in a switching manner; all bits of both the address input terminal and the external multiplex terminal are used to input information in the second generation form and the third generation form; and the predetermined bit string and the another particular bit array are input from the external multiplex terminal. ### Claim 7 (depends on 1) The data processing system according to claim 1, wherein the form of the address signal generated by the address control circuit includes: a fourth generation form in which, when particular bits of the address information input from the external terminal arrangement are a first value, the address information from the external terminal arrangement excluding the particular bits is defined as a lower portion and the upper portion is defined as the supplementary information held in the supplementary register with the upper portion further defined as a default value assigned to an address of a particular resource; and a fifth generation form in which, when particular bits of the address information input from the external terminal arrangement are a second value, a predetermined bit string of information from the external terminal arrangement is defined as the lower portion and the upper portion is defined as a default value assigned to an address of a resource corresponding to a value of another particular bit array of the information input from the external terminal arrangement. ### Claim 8 (depends on 7) The data processing system according to claim 7, wherein the particular resource is the memory device, and the resource corresponding to the value of the particular bit array is a group of registers built in the first data processor. ### Claim 9 (depends on 7) The data processing system according to claim 7, wherein the external terminal arrangement includes an external multiplex terminal and an address input terminal used for address input or data input/output in a switching manner, and wherein one bit of the address input terminal and all bits of the external multiplex terminal are used to input information in the fourth generation form and the fifth generation form; and the predetermined bit string and the another particular bit array are input from the external multiplex terminal. ### Claim 10 (depends on 9) The data processing system according to claim 9, further comprising: an incrementer which increments the supplementary information of the supplementary register; and an address increment control circuit which provides the incrementer with an instruction of an increment operation each time a value expressed by the number of bits of the address information from the external multiplex terminal to be supplemented by the supplementary register in the fourth generation form reaches a last value immediately before the value goes around. ### Claim 11 (depends on 10) The data processing system according to claim 10, wherein the address increment control circuit issues the instruction of an increment operation in response to the value of the address information from the external terminal arrangement being set to the last value immediately before a final value expressed by the number of bits of the address information according to a multibyte address increment mode in which the address information from the external terminal arrangement is varied in units of multibyte addresses. ### Claim 12 (depends on 11) The data processing system according to claim 11, further comprising: an address increment mode register which specifies a type of the address increment mode, wherein the address increment control circuit switches, according to the type specified in the address increment mode register, the final value when instructing an address increment operation. ### Claim 13 (depends on 2) The data processing system according to claim 2, wherein the form of the address signal generated by the address control circuit includes a sixth generation form in which the address information input from terminals of the external terminal arrangement with a smaller number of bits than that used in the first generation form is supplemented by supplementary information of the supplementary register having a larger number of bits than that used in the first generation form. ### Claim 14 (depends on 13) The data processing system according to claim 13, wherein the external terminal arrangement to which the address information is input in the sixth generation form includes an external multiplex terminal used for address input or data input/output in a switching manner. ### Claim 15 (depends on 14) The data processing system according to claim 14, further comprising: an incrementer which increments a value of the supplementary register; and an address increment control circuit which provides the incrementer with an instruction of an increment operation each time a value expressed by the number of bits of the address information from the external multiplex terminal to be supplemented by the supplementary register in the sixth generation form reaches a last value immediately before the value goes around. ### Claim 16 (depends on 15) The data processing system according to claim 15, wherein the address increment control circuit issues the instruction of an increment operation in response to the value of the address information from the external terminal arrangement being set to the last value immediately before a final value expressed by the number of bits of the address information according to a multibyte address increment mode in which the address information from the external terminal arrangement is varied in units of multibyte addresses. ### Claim 17 (depends on 16) The data processing system according to claim 16, further comprising: an address increment mode register which specifies a type of the address increment mode, wherein the address increment control circuit switches, according to the type specified in the address increment mode register, the final value when instructing an address increment operation.