Digital signal processing block with preadder stage

An integrated circuit, comprising:

• programmable logic blocks including at least a configurable logic block and a digital signal processing block;
• wherein each digital signal processing block is a dedicated circuit block including a preadder stage, a multiplier stage, an adder stage, internal routing circuitry, and a control bus;
• the control bus coupled to the preadder stage for dynamically controlling operation of the preadder stage;
• the preadder stage including:
• a first input port comprising a control port of a first multiplexer coupled to the control bus;
• a first register and a second register coupled in series via a second multiplexer to the first multiplexer;
• a second input port of a first logic gate coupled to the control bus;
• a third input port of a second logic gate coupled to the control bus;
• and
• a fourth input port of an adder/subtractor coupled to the control bus, wherein the first multiplexer enables coupling an output of the first register and an output of the second register to the adder/subtractor;
• wherein an output of the first logic gate and an output of the second logic gate are coupled to inputs of the adder/subtractor, an output of the adder/subtractor is coupled to the multiplier stage using the internal routing circuitry within the digital signal processing block, an output of the multiplier stage is coupled to the adder stage, and fixed logic values are dynamically provided to inputs of the adder/subtractor to enable dynamic power gating for power conservation.

A method of implementing a digital signal processor, the method comprising:

• providing programmable logic blocks including at least a configurable logic block and a digital signal processing block, where each digital signal processing block is a dedicated circuit block having a preadder stage, a multiplier stage, an adder stage, internal routing circuitry, and a control bus;
• coupling the control bus to the preadder stage for dynamically controlling operation of the preadder stage, wherein the preadder stage includes:
• a first input port comprising a control port of a first multiplexer coupled to the control bus;
• a first register and a second register coupled in series via a second multiplexer to the first multiplexer;
• a second input port of a first logic gate coupled to the control bus;
• a third input port of a second logic gate coupled to the control bus;
• and
• a fourth input port of an adder/subtractor coupled to the control bus, wherein the first multiplexer enables coupling an output of the first register and an output of the second register to the adder/subtractor, wherein the adder/subtractor is coupled to an output of the first logic gate and an output of the second logic gate, an output of the adder/subtractor is coupled to the multiplier stage using the internal routing circuitry within the digital signal processing block, and an output of the multiplier stage is coupled to the adder stage;
• and
• enabling power gating for power conservation by setting inputs to the adder/subtractor using the first logic gate and the second logic gate.