# US 8,543,369 B2 · Method and data processing system for simulating an embedded system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,543,369 B2 - Document ID: US8543369B2 - Status: Granted - Kind: B2 - Application number: 13/125,967 - Filed: 2009-12-23 - Published: 2012-02-02 - Granted: 2013-09-24 - Earliest claimed: 2009-12-23 - Assignees: Inchron GmbH - Applicants: Matthias Dörfel; Ralf Münzenberger - Inventors: Matthias Dörfel; Ralf Münzenberger - Web page: https://patentgrep.com/patent/US8543369B2 ## CPC - G06F 30/33: Design verification, e.g. functional simulation or model checking - G06F 11/3419: {by assessing time} - G06F 11/3457: {Performance evaluation by simulation} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract The invention relates to a computer-assisted method and data processing system for simulating an embedded system, wherein a plurality of hardware components, respectively provided with a software, are connected via a data exchange network for data exchange, wherein in a simulation program every component is simulated as a processing unit managing an amount of processes, wherein with the simulation program, a start time is dynamically assigned to every processing unit, wherein the processing units are successively sorted dynamically according to their start times, wherein the processing unit with the next start time is respectively selected via a scheduler, wherein, due to the selection of a processing unit, the respective active process is simulated by execution of a program code derived from a corresponding basic block graph and as a result of the simulation, the time required for the execution and/or information about the effected function is/are determined. ## Claims ### Claim 1 Computer-assisted method for simulating an embedded system, wherein a plurality of hardware components, respectively provided with a software, are connected via a data exchange network for data exchange, the method comprising: simulating components of the embedded system as a processing unit managing an amount of processes, dynamically assigning, with the simulation program, a start time to every processing unit, the start time being a point of time where the processing unit is selected and activated, successively sorting the processing units dynamically according to their start times, selecting a processing unit with the next start time via a scheduler, wherein, due to the selection of a processing unit, the respective active process is simulated by execution of a program code derived from a corresponding basic block graph and as a result of the simulation, a time required for the execution and/or information about a function effected by the simulation is/are determined. ### Claim 2 (depends on 1) The method according to claim 1, wherein every processing unit is assigned a clock simulation program and a local time required for the execution of a process is determined using the clock simulation program. ### Claim 3 (depends on 2) The method according to claim 2, wherein the local times are translated to the start times by using the system time. ### Claim 4 (depends on 1) The method according to claim 1, wherein every process is described by at least one basic block in the basic block graph. ### Claim 5 (depends on 1) The method according to claim 1, wherein the basic block is provided with information enabling the determination of the execution time necessary for the execution of the basic block and/or a function generated by the execution of the basic block. ### Claim 6 (depends on 1) The method according to claim 1, wherein the basic block graph containing the basic blocks is translated by means of a compiler to the program code. ### Claim 7 (depends on 1) The method according to claim 1, wherein the simulated embedded system uses one or more hierarchical schedulers. ### Claim 8 (depends on 1) The method according to claim 1, wherein following the execution of a program code section corresponding to a basic block, it is examined according to given parameters whether the next processing unit is to be selected by means of the scheduler and/or whether the active process is to be continued on the selected processing unit. ### Claim 9 (depends on 1) The method according to claim 1, wherein the simulation program has a first simulation program section comprising the processing units and a second simulation program section determining the execution time and/or the function. ### Claim 10 (depends on 1) The method according to claim 1, wherein the simulation program is executed on a host computer whose processor is identical or similar to a further processor of the embedded system. ### Claim 11 Computer program product having instructions stored on a non-transitory computer-readable data carrier executable by a computer, wherein the computer performs the computer-executable instructions when the program product is executed on the computer to perform a method comprising: simulating components of the embedded system as a processing unit managing an amount of processes, dynamically assigning, with the simulation program, a start time to every processing unit, the start time being a point of time where the processing unit is selected and activated, successively sorting the processing units dynamically according to their start times, selecting a processing unit with the next start time via a scheduler, wherein, due to the selection of a processing unit, the respective active process is simulated by execution of a program code derived from a corresponding basic block graph and as a result of the simulation, a time required for the execution and/or information about a function effected by the simulation is/are determined. ### Claim 12 Data processing system for simulating an embedded system, wherein a plurality of hardware components, respectively provided with a software, are connected via a data exchange network for data exchange, the data processing system comprising: a simulation program host computer that simulates every component as a processing unit managing an amount of processes, wherein the simulation program host computer dynamically assigns a start time to every processing unit, the start time being a point of time where the processing unit is selected and activated, a sorting unit configured for sorting the processing units dynamically according to their start times, a scheduler configured for selecting the processing unit with the next start time, wherein the data processing system simulates, due to the selection of a processing unit, the active process assigned to the processing unit by executing a program code derived from a corresponding basic block graph and as a result of the simulation, a time required for execution and/or an information about the function effected by the simulation is determined. ### Claim 13 (depends on 12) The data processing system according to claim 12, wherein every processing unit is assigned a clock simulation program and a local time required for the execution of a process is determined using the clock simulation program. ### Claim 14 (depends on 13) The data processing system according to claim 13, wherein the data processing system is adapted to translate the local times to the start times using the system time. ### Claim 15 (depends on 12) The data processing system according to claim 12, wherein every process is described by at least one basic block in the basic block graph. ### Claim 16 (depends on 12) The data processing system according to claim 12, wherein the basic block is provided with information enabling the determination of the execution time necessary for an execution of the basic block and/or the function generated by the execution of the basic block. ### Claim 17 (depends on 12) The data processing system according to claim 12, wherein the data processing system is adapted to translate the basic block graphs containing the basic blocks to the program code by means of a compiler. ### Claim 18 (depends on 12) The data processing system according to claim 12, wherein the simulated embedded system uses one or more hierarchical schedulers. ### Claim 19 (depends on 12) The data processing system according to claim 12, wherein the data processing system is adapted to examine, following the execution of a program code section corresponding to a basic block, according to given parameters whether the next processing unit is to be selected by means of the scheduler and/or whether the active process is to be continued on the selected processing unit. ### Claim 20 (depends on 12) The data processing system according to claim 12, wherein the simulation program has a first simulation program section comprising the processing units and a second simulation program section determining the execution time and/or the function. ### Claim 21 (depends on 12) The data processing system according to claim 12, wherein the simulation program is carried out on a host computer whose processor is identical or similar to a further processor of the embedded system.