# US 8,542,787 B2 · Phase adjustment apparatus and method for a memory device signaling system

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- Number: US 8,542,787 B2
- Document ID: US8542787B2
- Status: Granted
- Kind: B2
- Application number: 13/163,618
- Filed: 2011-06-17
- Published: 2011-10-13
- Granted: 2013-09-24
- Earliest claimed: 2001-10-22
- Assignees: Rambus Inc.
- Applicants: Craig E. Hampel; Richard E. Perego; Stefanos S. Sidiropoulos; Ely K. Tsern; Fredrick A. Ware
- Inventors: Craig E. Hampel; Richard E. Perego; Stefanos S. Sidiropoulos; Ely K. Tsern; Fredrick A. Ware
- Web page: https://patentgrep.com/patent/US8542787B2

## CPC

- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G06F 3/061: {Improving I/O performance}
- G06F 3/0629: {Configuration or reconfiguration of storage systems}
- G06F 3/0671: {In-line storage system}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C 7/1051: {Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits}
- G11C 7/106: {Data output latches}
- G11C 7/1066: {Output synchronization}
- G11C 7/1078: {Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits}
- G11C 7/1087: {Data input latches}
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 11/40611: {External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh}
- G11C 11/4072: Circuits for initialization, powering up or down, clearing memory or presetting
- G11C 11/4078: Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells (protection of memory contents during checking or testing G11C29/52)
- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G11C 21/00: Digital stores in which the information circulates {continuously}(stepwise G11C19/00)
- H04L 7/0091: {Transmitter details}
- G11C 2207/2254: Calibration
- H04L 7/0025: {interpolation of clock signal}
- H04L 7/0079: {Receiver details}
- H04L 67/10: in which an application is distributed across nodes in the network (software deployment G06F8/60; multiprogramming arrangements G06F9/46)
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Apparatus and methods are disclosed for adjusting phase of data signals to compensate for phase-offset variations between devices during normal operation. The phase of data signals are adjusted individually in each transmit data unit and receive data unit across multiple data slices with a common set of phase vector clock signals and a corresponding clock cycle count signal. The transmission of signal information between a first device (such as a memory controller) and a second device (such as a memory component) occurs without errors even when the accumulated delays between the first device and second device change by a half symbol time interval or more during operation of the system. The apparatus reduces the circuitry required, such as phase-lock-loops, for individually adjusting the phase of each transmit data unit and receive data unit across multiple data slices, which in turn results in reduction in complexity and cost of the system.

## Claims

### Claim 1

An integrated circuit device comprising:
a clock generator circuit to generate a plurality of phase vector clock signals;
a receiver phase adjuster to generate a receiver clock with a phase determined in accordance with a combination of a set of at least two phase vector clock signals of the plurality of phase vector clock signals;
a transmit phase adjuster to generate a transmit clock with a phase determined in accordance with a combination of a set of at least two phase vector clock signals of the plurality of phase vector clock signals;
an input sampling circuit configured to time receiving of receive data in accordance with the phase of the receiver clock; and
an output circuit configured to time transmission of transmit data in accordance with the phase of the transmit clock.

### Claim 2 (depends on 1)

The device of claim 1, wherein:
the plurality of phase vector clock signals comprise a group of evenly phase shifted clock signals; and
the transmit data and the receive data are signals selected from the set consisting of:
differential pairs of signals and single-ended signals.

### Claim 3 (depends on 1)

The device of claim 1, wherein the input sampling circuit comprises a serial-to-parallel-conversion circuit including a set of serially connected registers clocked by the receiver clock, the serial-to-parallel-conversion circuit having at least a first register configured to provide receive data to circuitry internal to the device.

### Claim 4 (depends on 1)

The device of claim 1, wherein the output circuit comprises a parallel-to-serial-conversion circuit including a set of serially connected registers clocked by the transmit clock, the parallel-to-serial-conversion circuit having at least a first register configured to provide transmit data to an interface of the device.

### Claim 5 (depends on 1)

The device of claim 1, further including a transmit skip circuit, coupled to the output circuit, the transmit skip circuit configured to provide the transmit data to the output circuit at a phase relative to a local clock determined in accordance with a digitally stored transmit skip value.

### Claim 6 (depends on 5)

The device of claim 5, further including a receive skip circuit, coupled to the input sampling circuit, the receive skip circuit configured to transfer the receive data from the input sampling circuit to a next circuit at a phase relative to a local clock determined in accordance with a digitally stored receive skip value.

### Claim 7 (depends on 6)

The device of claim 6, wherein the receive skip circuit comprises:
a first receive skip latch for receiving and latching the receive data in response to the receiver clock;
a second receive skip latch for latching the receive data, as output by the first receive skip latch, in response to the local clock; and
a multiplexer having inputs coupled to outputs of the first and second receive skip latches and an output coupled to the next circuit, wherein the multiplexer selects among the first and second latch outputs in accordance with the digitally stored receive skip value.

### Claim 8 (depends on 1)

The device of claim 1, wherein the phase of the receiver clock is determined in accordance with a digitally stored receiver phase value that specifies parameters for combining the set of phase vector clock signals for the receiver clock.

### Claim 9 (depends on 8)

The device of claim 8, wherein the digitally stored receiver phase value comprises:
a receiver phase-select value for use in selecting the set of phase vector clock signals for the receiver clock; and
a receiver phase-blend value for use in controlling interpolation of the selected set of phase vector clock signals for the receiver clock.

### Claim 10 (depends on 9)

The device of claim 9, wherein the receiver phase adjuster comprises:
a selection circuit configured to select the set of phase vector clock signals for the receiver clock in accordance with the receiver phase-select value; and
a phase interpolator unit configured to interpolate between the set of phase vector clock signals for the receiver clock to generate the receiver clock having a phase between phases of the set of phase vector clock signals for the receiver clock in accordance with the receiver phase-blend value.

### Claim 11 (depends on 10)

The device of claim 10, wherein the selection circuit comprises a reference phase selection unit and a set of multiplexer units for selecting the set of phase vector clock signals for the receiver clock.

### Claim 12 (depends on 9)

The device of claim 9, wherein the digitally stored receiver phase value further comprises a receiver load-cycle value for use in controlling clock cycle timing for loading of the receive data.

### Claim 13 (depends on 1)

The device of claim 1, wherein the phase of the transmit clock is determined in accordance with a digitally stored transmit phase value that specifies parameters for combining the set of phase vector clock signals for the transmit clock.

### Claim 14 (depends on 13)

The device of claim 13, wherein the digitally stored transmit phase value comprises:
a transmit phase-select value for use in selecting the set of phase vector clock signals for the transmit clock; and
a transmit phase-blend value for use in controlling interpolation of the selected set of phase vector clock signals for the transmit clock.

### Claim 15 (depends on 14)

The device of claim 14, wherein the transmit phase adjuster comprises:
a selection circuit configured to select the set of phase vector clock signals for the transmit clock in accordance with the transmit phase-select value; and
a phase interpolator unit configured to interpolate between the set of phase vector clock signals for the transmit clock to generate the transmit clock having a phase between phases of the set of phase vector clock signals for the transmit clock in accordance with the transmit phase-blend value.

### Claim 16 (depends on 15)

The device of claim 15, wherein the selection circuit comprises a reference phase selection unit and a set of multiplexer units for selecting the set of phase vector clock signals for the transmit clock.

### Claim 17 (depends on 14)

The device of claim 14, wherein the digitally stored transmit phase value further comprises a transmit load-cycle value for use in controlling clock cycle timing for loading of the transmit data.

### Claim 18

A method, performed by an integrated circuit device, the method comprising:
generating a plurality of phase vector clock signals;
generating a receiver clock with a phase determined in accordance with a combination of a set of at least two phase vector clock signals of the plurality of phase vector clock signals;
generating a transmit clock with a phase determined in accordance with a combination of a set of at least two phase vector clock signals of the plurality of phase vector clock signals;
receiving receive data with receive timing in accordance with the phase of the receiver clock;
transmitting transmit data with transmit timing in accordance with the phase of the transmit clock.

### Claim 19 (depends on 18)

The method of claim 18, wherein:
the plurality of phase vector clock signals comprise a group of evenly phase shifted clock signals; and
the transmit data and the receive data are signals selected from the set consisting of:
differential pairs of signals and single-ended signals.

### Claim 20 (depends on 18)

The method of claim 18, wherein receiving the receive data includes converting the receive data from serial data to parallel data.

### Claim 21 (depends on 18)

The method of claim 18, wherein transmitting the transmit data includes converting the transmit data from parallel data to serial data.

### Claim 22 (depends on 18)

The method of claim 18, wherein the transmit data is transmitted at a phase relative to a local clock determined in accordance with a digitally stored transmit skip value.

### Claim 23 (depends on 22)

The method of claim 22, wherein the receive data is received at a phase relative to the local clock determined in accordance with a digitally stored receive skip value.

### Claim 24 (depends on 23)

The method of claim 23, further comprising:
latching the receive data in response to the receiver clock to generate a first latch output;
latching the first latch output in response to the local clock to generate a second latch output; and
selecting among the first and second latch outputs in accordance with the digitally stored receive skip value.

### Claim 25 (depends on 18)

The method of claim 18, wherein the phase of the receiver clock is determined in accordance with a digitally stored receiver phase value that specifies parameters for combining the set of phase vector clock signals for the receiver clock.

### Claim 26 (depends on 25)

The method of claim 25, wherein the digitally stored receiver phase value comprises:
a receiver phase-select value for use in selecting the set of phase vector clock signals for the receiver clock; and
a receiver phase-blend value for use in controlling interpolation of the selected set of phase vector clock signals for the receiver clock.

### Claim 27 (depends on 26)

The method of claim 26, wherein generating the receiver clock comprises:
selecting the set of phase vector clock signals for the receiver clock in accordance with the receiver phase-select value; and
interpolating between the set of phase vector clock signals for the receiver clock to generate the receiver clock having a phase between phases of the set of phase vector clock signals for the receiver clock in accordance with the receiver phase-blend value.

### Claim 28 (depends on 26)

The method of claim 26, wherein the digitally stored receiver phase value further comprises a receiver load-cycle value for use in controlling clock cycle timing for loading of the receive data.

### Claim 29 (depends on 18)

The method of claim 18, wherein the phase of the transmit clock is determined in accordance with a digitally stored transmit phase value that specifies parameters for combining the set of phase vector clock signals for the transmit clock.

### Claim 30 (depends on 29)

The method of claim 29, wherein the digitally stored transmit phase value comprises:
a transmit phase-select value for use in selecting the set of phase vector clock signals for the transmit clock; and
a transmit phase-blend value for use in controlling interpolation of the selected set of phase vector clock signals for the transmit clock.

### Claim 31 (depends on 30)

The method of claim 30, generating the transmit clock comprises:
selecting the set of phase vector clock signals for the transmit clock in accordance with the transmit phase-select value; and
interpolating between the set of phase vector clock signals for the transmit clock to generate the transmit clock having a phase between phases of the set of phase vector clock signals for the transmit clock in accordance with the transmit phase-blend value.

### Claim 32 (depends on 30)

The method of claim 30, wherein the digitally stored transmit phase value further comprises a transmit load-cycle value for use in controlling clock cycle timing for loading of the transmit data.

### Claim 33

An integrated circuit device comprising:
a clock generator circuit to generate a plurality of phase vector clock signals;
a first circuit to generate a receiver clock with a phase that is interpolated from a first set of phase vector clock signals of the plurality of phase vector clock signals;
a second circuit to generate a transmit clock with a phase that is interpolated from a second set of phase vector clock signals of the plurality of phase vector clock signals;
an input sampling circuit configured to time receiving of receive data in accordance with the phase of the receiver clock; and
an output circuit configured to time transmission of transmit data in accordance with the phase of the transmit clock.

### Claim 34

A method, performed by an integrated circuit device, the method comprising:
generating a plurality of phase vector clock signals;
interpolating between a first set of the phase vector clock signals to generate a receiver clock;
interpolating between a second set of the phase vector clock signals to generate a transmit clock;
receiving receive data with receive timing in accordance with a phase of the receiver clock;
transmitting transmit data with transmit timing in accordance with a phase of the transmit clock.