# US 8,542,779 B2 · Receiver architecture and methods for demodulating binary phase shift keying signals

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- Number: US 8,542,779 B2
- Document ID: US8542779B2
- Status: Granted
- Kind: B2
- Application number: 13/754,819
- Filed: 2013-01-30
- Published: 2013-08-01
- Granted: 2013-09-24
- Earliest claimed: 2012-01-31
- Assignees: Innophase, Inc.
- Applicants: Innophase Inc.
- Inventors: Yang Xu
- Web page: https://patentgrep.com/patent/US8542779B2

## CPC

- H04L 27/2272: {using phase locked loops (H04L27/2273 takes precedence)}
- H04L 27/2071: {in which the data are represented by the carrier phase, e.g. systems with differential coding}
- H04L 27/22: Demodulator circuits; Receiver circuits
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A receiver is described. The receiver includes a first injection-locked oscillator having a first input configured to receive a BPSK signal and a second input configured to receive a first frequency reference. The receiver also includes a second injection-locked oscillator having a third input configured to receive the BPSK signal and a fourth input configured to receive a second frequency reference. Further, the receiver includes a first phase-locked loop coupled with the second input of the first injection-locked oscillator. The first phase-locked loop is configured to generate the first frequency reference. And, a second phase-locked loop is coupled with the fourth input of the second injection-locked oscillator. The second phase-locked loop is configured to generate the second frequency reference.

## Claims

### Claim 1

A receiver comprising:
a first injection-locked oscillator (ILO) having a first input configured to receive a binary phase shift keying (“BPSK”) signal and a second input configured to receive a first reference input to control an initial resonance frequency of the first ILO;
a second injection-locked oscillator (ILO) having a third input configured to receive said BPSK signal and a fourth input configured to receive a second reference input to control an initial resonance frequency of the second ILO;
a first ILO control circuit coupled with said second input of said first ILO, said first ILO control circuit configured to generate said first reference input; and
a second ILO control circuit coupled with said fourth input of said second ILO, said second ILO control circuit configured to generate said second reference input; and
a finite state machine coupled with said first ILO control circuit and coupled with said second ILO control circuit.

### Claim 2 (depends on 1)

The receiver of claim 1 further comprising a mixer coupled with said first ILO and said second ILO.

### Claim 3 (depends on 1)

The receiver of claim 1, wherein said finite state machine is coupled with said first ILO control circuit by a control signal.

### Claim 4 (depends on 3)

The receiver of claim 3, wherein said control signal adjusts a divide factor of said first ILO control circuit.

### Claim 5 (depends on 1)

The receiver of claim 1, wherein said finite state machine includes at least one of a state selected from the group consisting of: channel detection, clear channel assessment, data transmission, PVT calibration, receiver wake-up, and receiver power-down.

### Claim 6 (depends on 1)

The receiver of claim 1, wherein at least one of said first ILO control circuit and said second ILO control circuit is an analog ILO control circuit.

### Claim 7 (depends on 1)

The receiver of claim 1, wherein at least one of said first ILO control circuit or said second ILO control circuit is a digital ILO control circuit.

### Claim 8 (depends on 1)

The receiver of claim 1, wherein said first ILO control circuit is configured to receive a first output of said first ILO and said first reference input is based at least on said first output of said first ILO.

### Claim 9 (depends on 1)

The receiver of claim 1, wherein said first reference input tunes said first ILO to a frequency greater than one half of a carrier frequency of said BPSK signal and said second reference input tunes said second ILO to a frequency less than one half of said carrier frequency of said BPSK signal.

### Claim 10 (depends on 1)

The receiver of claim 1 further comprising an amplifier having a positive output and a negative output, said positive output coupled with said first ILO and said negative output coupled with said second ILO.

### Claim 11

A receiver comprising:
a first injection-locked oscillator (ILO) having a first input configured to receive a binary phase shift keying (“BPSK”) signal, a first ILO variable capacitor to change a resonant frequency of the first ILO, and a second input configured to receive a first control input for controlling the first ILO variable capacitor;
a second injection-locked oscillator (ILO) having a third input configured to receive said BPSK signal, a second ILO variable capacitor to change a resonant frequency of the second ILO, and a fourth input configured to receive a second control input for controlling the second ILO variable capacitor;
a digital control logic circuit having a channel selection input, a first ILO control circuit and a second ILO control circuit;
the first ILO control circuit coupled with said second input of said first ILO, said first ILO control circuit configured to generate said first control input; and
the second ILO control circuit coupled with said fourth input of said second ILO, said second ILO control circuit configured to generate said second control input; and,
the first ILO control circuit configured to adjust the resonant frequency of the first ILO by a positive frequency offset and the second ILO control circuit configured to adjust the resonant frequency of the second ILO by a negative frequency offset, where the positive frequency offset and the negative frequency offset are determined according to a data rate of the BPSK signal.

### Claim 12 (depends on 11)

The receiver of claim 11 further comprising a mixer coupled with said first ILO and said second ILO oscillator.

### Claim 13 (depends on 12)

The receiver of claim 12 comprising a finite state machine coupled with said first ILO control circuit and coupled with said second ILO control circuit.

### Claim 14 (depends on 13)

The receiver of claim 13, wherein said finite state machine is coupled with said first ILO control circuit by a control signal.

### Claim 15 (depends on 14)

The receiver of claim 14, wherein said control signal adjusts a tuning constant of said first ILO control circuit.

### Claim 16 (depends on 11)

The receiver of claim 11, wherein at least one of said first ILO control circuit and said second injection-locked oscillator control circuit is a phase-locked loop.

### Claim 17 (depends on 11)

The receiver of claim 11, wherein at least one of said first ILO control circuit and said second ILO control circuit is a frequency-locked loop.

### Claim 18 (depends on 11)

The receiver of claim 11, wherein said first ILO control circuit is configured to receive a first output of said first ILO and said first control input is based at least on said first output of said first ILO.

### Claim 19 (depends on 11)

The receiver of claim 11, wherein said first control input tunes the first ILO to a frequency greater than one half a carrier frequency of said BPSK signal and said second control input tunes the second ILO to a frequency less than one half said carrier frequency of said BPSK signal.

### Claim 20 (depends on 11)

The apparatus of claim 11 wherein the positive frequency offset and the negative frequency offset are between ½ and ⅛ of the data rate of the BPSK signal.

### Claim 21

A method for demodulating comprising:
receiving a channel selection input signal;
tuning a receiver to a selected channel by controlling a resonant frequency of a first injection-locked oscillator (ILO) to a frequency above one half of a carrier frequency of the selected channel, and controlling a resonant frequency of a second injection-locked oscillator (ILO) to a frequency below one half of the carrier frequency of the selected channel;
receiving a binary phase shift keyed signal;
generating a first channel based on said binary phase shift keyed signal;
generating a second channel based on said binary phase shift keyed signal;
processing said first channel using a first circuit including the first ILO coupled with a first ILO control circuit to generate a first output;
processing said second channel using a second circuit including a second ILO coupled with a second ILO control circuit to generate a second output; and
multiplying said first output with said second output.

### Claim 22 (depends on 21)

The method of claim 21 wherein controlling a resonant frequency of a first ILO and controlling a resonant frequency of a second ILO is performed by adjusting variable capacitors within the first and second ILOs, respectively.

### Claim 23 (depends on 22)

The method of claim 22 wherein adjusting variable capacitors is performed by (i) adjusting a voltage to a varactor or (ii) by providing binary control signals to a digitally tuned capacitor, or both (i) and (ii).

### Claim 24

A receiver comprising:
a first injection-locked oscillator (ILO) having a first input configured to receive a binary phase shift keying (“BPSK”) signal and a second input configured to receive a first ILO resonant frequency control signal;
a second injection-locked oscillator (ILO) having a third input configured to receive said BPSK signal and a fourth input configured to receive a second ILO resonant frequency control signal;
a first control logic circuit coupled with said second input of said first ILO, said first control logic circuit configured to generate said first ILO resonant frequency control signal; and
a second control logic circuit coupled with said fourth input of said second ILO, said second control logic circuit configured to generate said second ILO resonant frequency control signal; and,
an amplifier having a positive output and a negative output, said positive output coupled with said first ILO and said negative output coupled with said second ILO.

### Claim 25 (depends on 24)

The receiver of claim 24 wherein the first and second control logic circuit are configured to generate the first and second ILO resonant frequency control signals, respectively, based on frequency differences between a reference signal and outputs of the respective first and second ILOs.

### Claim 26 (depends on 25)

The receiver of claim 25 wherein the reference signal is provided by a frequency divider circuit.

### Claim 27 (depends on 26)

The receiver of claim 26 further comprising a finite state machine configured to adjust a divide factor of the frequency divider circuit.

### Claim 28 (depends on 26)

The receiver of claim 26 further comprising a phase-frequency detector configured to determine the frequency differences.