# US 8,542,773 B2 · Digital RF converter, digital RF modulator and transmitter including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,542,773 B2 - Document ID: US8542773B2 - Status: Granted - Kind: B2 - Application number: 12/968,731 - Filed: 2010-12-15 - Published: 2011-06-23 - Granted: 2013-09-24 - Earliest claimed: 2009-12-18 - Assignees: Electronics and Telecommunications Research Institute - Applicants: Hyun Kyu Yu; Jang Hong Choi; Hyun Ho Boo; Pil Jae Park; Mun Yang Park; Seong Do Kim; Sun Bo Shim; Song Cheol Hong - Inventors: Hyun Kyu Yu; Jang Hong Choi; Hyun Ho Boo; Pil Jae Park; Mun Yang Park; Seong Do Kim; Sun Bo Shim; Song Cheol Hong - Web page: https://patentgrep.com/patent/US8542773B2 ## CPC - H03M 1/68: with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits - H03M 1/687: {Segmented, i.e. the more significant bit converter being of the unary decoded type and the less significant bit converter being of the binary weighted type} - H03M 1/745: {with weighted currents} - H03M 1/747: {with equal currents which are switched by unary decoded digital signals} - H03M 3/50: {Digital/analogue converters using delta-sigma modulation as an intermediate step (digital delta-sigma modulators per se H03M7/3004)} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract A digital RF converter, a digital RF modulator, and a transmitter are provided. The digital RF converter includes a delta-sigma modulated bits (DSMB) sub-block that generates a current magnitude corresponding to least-significant n bits among input signals at a first sampling speed, a least-significant bit (LSB) sub-block that generates a current magnitude corresponding to intermediate k bits among the input signals at a second sampling speed lower than the first sampling speed, and a most-significant bit (MSB) sub block that generates a current magnitude corresponding to most-significant m bits among the inputs signals at the second sampling speed. ## Claims ### Claim 1 A digital RF converter, comprising: a delta-sigma modulated bits (DSMB) sub-block configured to generate a current magnitude corresponding to least-significant n bits among input signals at a first sampling frequency; a least-significant bit (LSB) sub-block configured to generate a current magnitude corresponding to intermediate k bits among the input signals at a second sampling frequency lower than the first sampling frequency; and a most-significant bit (MSB) sub-block configured to generate a current magnitude corresponding to most-significant m bits among the inputs signals at the second sampling frequency. ### Claim 2 (depends on 1) The digital RF converter of claim 1, wherein the least-significant n bits are signals that are sigma-delta modulated, oversampled, and noise-shaped. ### Claim 3 (depends on 2) The digital RF converter of claim 2, wherein the first sampling frequency is substantially the same as a sigma-delta modulation frequency. ### Claim 4 (depends on 1) The digital RF converter of claim 1, wherein the DSMB sub-block includes: 2n−1 cells having a minimum current magnitude; and 2n−1 latches configured to provide the least-significant n bits to the 2n−1 cells at the first sampling frequency to vary an amount of current flowing through the 2n−1 cells. ### Claim 5 (depends on 4) The digital RF converter of claim 4, wherein the LSB sub-block includes: k cells having a current magnitude of 2k−1I (where k is a natural number, k represents the number of cells included in the LSB sub-block, and I represents the minimum current magnitude); and k latches configured to provide the intermediate k bits to the k cells at the second sampling frequency to vary an amount of current flowing through the k cells. ### Claim 6 (depends on 4) The digital RF converter of claim 4, wherein the MSB sub-block includes: 2m−1 cells having a current magnitude of 2kI (where k represents the number of cells included in the LSB sub-block and I represents the minimum current magnitude); and 2m−1 latches configured to provide the most-significant m bits to the 2m−1 cells at the second sampling frequency to vary an amount of current flowing through the 2m−1 cells. ### Claim 7 A digital RF modulator, comprising: a pulse shaping digital filter configured to receive digital signals of a baseband and pulse-shape only digital signals included in a communication bandwidth; a sigma-delta modulator configured to perform sigma-delta modulation on least-significant n bits among the pulse-shaped signals; a decoder configured to decode the sigma-delta modulated n bits to a thermometer code, decode the intermediate k bits among the pulse shaped signals to a binary code, and decode the most-significant m bits among the pulse-shaped signals to a thermometer code; and a digital RF converter configured to segment the decoded n bits, the decoded k bits, and the decoded m bits and perform digital-to-analog conversion thereon, perform the digital-to-analog conversion on the decoded n bits at the same sampling frequency as that of the sigma-delta modulator, and perform the digital-to-analog conversion on the decoded k bits and m bits at a sampling frequency lower than that of the sigma-delta modulator. ### Claim 8 (depends on 7) The digital RF modulator of claim 7, wherein the digital RF converter includes: a delta-sigma modulated bits (DSMB) sub-block configured to generate a current magnitude corresponding to the decoded n bits at the same sampling frequency as that of the sigma-delta modulator; a least-significant bit (LSB) sub-block configured to generate a current magnitude corresponding to the decoded k bits at a sampling frequency lower than that of the sigma-delta modulator; and a most-significant bit (MSB) sub-block configured to generate a current magnitude corresponding to the decoded m bits at a sampling frequency lower than that of the sigma-delta modulator. ### Claim 9 (depends on 8) The digital RF modulator of claim 8, wherein the DSMB sub-block includes: 2n−1 cells having a minimum current magnitude; and 2n−1 latches configured to provide the decoded n bits to the 2n−1 cells at the same sampling frequency as that of the sigma-delta modulator to vary an amount of current flowing through the 2n−1 cells. ### Claim 10 (depends on 9) The digital RF modulator of claim 9, wherein the LSB sub-block includes: k cells having a current magnitude of 2k−1I (where k is a natural number, k represents the number of cells included in the LSB sub-block, and I represents the minimum current magnitude); and k latches configured to provide the decoded k bits to the k cells at a sampling frequency lower than that of the sigma-delta modulator to vary an amount of current flowing through the k cells. ### Claim 11 (depends on 9) The digital RF modulator of claim 9, wherein the MSB sub-block includes: 2m−1 cells having a current magnitude of 2kI (where k represents the number of cells included in the LSB sub-block and I represents the minimum current magnitude); and 2m−1 latches configured to provide the decoded m bits to the 2m−1 cells at the sampling frequency lower than that of the sigma-delta modulator to vary an amount of current flowing through the 2m−1 cells. ### Claim 12 (depends on 7) The digital RF modulator of claim 7, further comprising a delay correction circuit configured to synchronize the intermediate k bits among the pulse-shaped signals and the most-significant m bits among the pulse-shaped signals with the sigma-delta modulated n bits, and input the synchronized k bits and m bits to the decoder. ### Claim 13 A direct up conversion transmitter, comprising: a first digital RF modulator configured to modulate and output certain bits of in-phase signals at a different sampling frequency than remaining bits of the in-phase signals; a second digital RF modulator configured to modulate and output certain bits of quadrature signals at a different sampling frequency than remaining bits of the quadrature signals; a carrier signal generator configured to generate carrier signals required to modulate the in-phase signals and the quadrature signals; a differential-single output converter configured to convert the modulated in-phase signals and quadrature signals into a single output signal; a filter configured to remove cosine signals and spurious waves included in the single output signal; and a power amplifier configured to amplify and output the power of the filtered signal. ### Claim 14 (depends on 13) The direct up conversion transmitter of claim 13, wherein each of the first and second digital RF modulators includes: a pulse shaping digital filter configured to receive the in-phase signals or the quadrature signals and pulse-shape only the digital signals included in a communication bandwidth; a sigma-delta modulator configured to perform sigma-delta modulation on least-significant n bits among the pulse-shaped signals; a decoder configured to decode the sigma-delta modulated n bits to a thermometer code, decode the intermediate k bits among the pulse shaped signals to a binary code, and decode the most-significant m bits among the pulse-shaped signals to a thermometer code; and a digital RF converter configured to segment the decoded n bits, the decoded k bits, and the decoded m bits and perform digital-to-analog conversion thereon, perform the digital-to-analog conversion on the decoded n bits at the same sampling frequency as that of the sigma-delta modulator, and perform the digital-to-analog conversion on the decoded k bits and m bits at the sampling frequency lower than that of the sigma-delta modulator. ### Claim 15 (depends on 14) The direct up conversion transmitter of claim 14, wherein the digital RF converter includes: a delta-sigma modulated bits (DSMB) sub-block configured to generate a current magnitude corresponding to the decoded n bits at the same sampling frequency as that of the sigma-delta modulator; a least-significant bit (LSB) sub-block configured to generate a current magnitude corresponding to the decoded k bits at the sampling frequency lower than that of the sigma-delta modulator; and a most-significant bit (MSB) sub-block configured to generate a current magnitude corresponding to the decoded m bits at the sampling frequency lower than that of the sigma-delta modulator.