# US 8,542,764 B2 · Power and area efficient SerDes transmitter

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- Number: US 8,542,764 B2
- Document ID: US8542764B2
- Status: Granted
- Kind: B2
- Application number: 12/353,717
- Filed: 2009-01-14
- Published: 2010-07-15
- Granted: 2013-09-24
- Earliest claimed: 2009-01-14
- Assignees: Sun Microsystems, Inc.
- Applicants: Dong J. Yoon; Dawei Huang; Drew G. Doblar
- Inventors: Dong J. Yoon; Dawei Huang; Drew G. Doblar
- Web page: https://patentgrep.com/patent/US8542764B2

## CPC

- H03M 9/00: Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00)
- H03K 3/00: Circuits for generating electric pulses; Monostable, bistable or multistable circuits (H03K4/00 takes precedence; for digital function generators in computers G06F1/02)
- H03L 7/0814: {the phase shifting device being digitally controlled}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

A system and method include a SerDes transmitter comprising a digital block operating in a digital voltage domain. The digital block can be configured to receive a first group of bits of data in parallel and store history bits from another group of data. The SerDes transmitter can further comprise an analog block operating in an analog voltage domain. The analog block can be configured to receive the first group of bits of data from the digital block, receive the history bits from the digital block, generate a plurality of combinations of bits with one or more bits from the first group of bits and zero or more bits from the history bits, align each combination of bits to a phase of a multi-phase clock; and input each combination into an output driver.

## Claims

### Claim 1

A transmitter comprising: a digital block operating in a digital voltage domain, the digital block comprising:
a first storage element to store a first group of bits of data in parallel; and
a second storage element to store history bits from another group of data; and
an analog block operating in an analog voltage domain, the analog block comprising:
circuitry to receive the first group of bits of data from the digital block;
circuitry to receive the history bits from the digital block;
circuitry to generate a plurality of combinations of bits with one or more bits from the first group of bits and zero or more bits from the history bits;
phase alignment circuitry to align each combination of bits to a phase of a clock; and
an output driver to produce an output signal in response to receiving each combination.

### Claim 2 (depends on 1)

The transmitter of claim 1, wherein the analog block receives each bit from the first group of bits and each bit from the history bits once during a digital clock cycle.

### Claim 3 (depends on 1)

The transmitter of claim 1, wherein the first group of bits and the history bits are sent from the digital block to the analog block aligned to a single-phase clock.

### Claim 4 (depends on 1)

The transmitter of claim 1, wherein the digital block operates on a single-phase clock.

### Claim 5 (depends on 1)

The transmitter of claim 1, wherein the datapath from the digital block to the analog block is the width of the number of bits in the history bits and the first group of bits.

### Claim 6 (depends on 1)

The transmitter of claim 1, wherein the history bits comprise post-cursor bits and pre-cursor bits.

### Claim 7 (depends on 1)

The transmitter of claim 1, wherein the output driver generates output signals in accordance with tap weightings applied to each bit in each combination of bits.

### Claim 8 (depends on 1)

The transmitter of claim 1, wherein the clock is a multi-phase clock.

### Claim 9 (depends on 1)

The transmitter of claim 1, wherein the clock is a single-phase clock.

### Claim 10

A transmitter comprising: a digital block operating in a digital voltage domain, the digital block comprising:
a first storage element to store a first group of bits;
a second storage element to receive from the first storage element a second group of bits; and
an analog block operating in an analog voltage domain, the analog block comprising:
phase alignment circuitry to receive the first group of bits from the first storage element and the second group of bits from the second storage element, wherein a width of a datapath between the first and second storage elements and the phase alignment circuitry is equal to a total number of bits in the first and second groups of bits; and
an output driver comprising a plurality of staging flops, the output driver configured to receive different combinations of bits from the first and second groups of bits,
wherein the different combinations of bits comprises one or more bits from the first group of bits and zero or more bits from the second group of bits.

### Claim 11 (depends on 10)

The transmitter of claim 10, wherein the phase alignment circuitry receives each bit from the first and second groups of bits once during a digital clock cycle.

### Claim 12 (depends on 10)

The Transmitter of claim 10, wherein the first and second group of bits are sent in parallel from the first and second storage elements to the phase alignment circuitry.

### Claim 13 (depends on 10)

The transmitter of claim 10, wherein the first and second group of bits are aligned to a single phase clock when sent from the first and second storage elements to the phase alignment circuitry.

### Claim 14 (depends on 10)

The transmitter of claim 10, wherein the output driver generates output signals in accordance with tap weightings applied to each bit within the combinations of bits.

### Claim 15 (depends on 10)

The transmitter of claim 10, wherein the phase alignment circuitry is to align each different combination of bits to a phase of a multi-phase clock and the output driver is to output pulses aligned to the phases of the multi-phase clock.

### Claim 16 (depends on 10)

The transmitter of claim 10, wherein the phase alignment circuitry is to align each different combination of bits to a phase of a single-phase clock and the output driver is to output pulses aligned to the phases of the single-phase clock.

### Claim 17

A method comprising:
receiving a first group of bits of parallel data in a digital block;
storing history bits in the digital block;
transferring the first group of bits and the history bits from the digital block to an analog block;
generating in the analog block a plurality of combinations of bits, each combination comprising one or more bits from the first group of bits and zero or more bits from the history bits;
aligning a first combination from the plurality of combinations of bits to a phase of a clock; and
inputting the first combination into an output driver to produce an output signal.

### Claim 18 (depends on 17)

The method of claim 17, wherein the digital block operates on a single-phase clock.

### Claim 19 (depends on 17)

The method of claim 17, wherein a datapath from the digital block to the analog block is the width of the number of bits in the history bits and the first group of bits.

### Claim 20 (depends on 17)

The method of claim 17, wherein the output driver generates output signals in accordance with tap weightings applied to each bit in the first combination.

### Claim 21

A system comprising:
a first electronic component comprising a receiver;
a connector;
a second electronic component comprising a transmitter configured to transmit data to the first electronic component via the connector, the transmitter comprising:
a digital block operating in a digital voltage domain, the digital block comprising:
a first storage element to store a first group of bits of data in parallel; and
a second storage element to store history bits from another group of data; and
an analog block operating in an analog voltage domain, the analog block comprising:
circuitry to receive the first group of bits of data from the digital block;
circuitry to receive the history bits from the digital block;
circuitry to generate a plurality of combinations of bits with one or more bits from the first group of bits and zero or more bits from the history bits;
phase alignment circuitry to align each combination of bits to a phase of a clock; and
an output driver to produce an output signal in response to receiving each combination.