# US 8,542,755 B2 · Time accurate control of RF over a digrf interface

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- Number: US 8,542,755 B2
- Document ID: US8542755B2
- Status: Granted
- Kind: B2
- Application number: 12/540,194
- Filed: 2009-08-12
- Published: 2010-03-25
- Granted: 2013-09-24
- Earliest claimed: 2008-08-12
- Assignees: ST-Ericsson SA
- Applicants: Rob Kopmeiners; Jeroen Cornelis Kuenen
- Inventors: Rob Kopmeiners; Jeroen Cornelis Kuenen
- Web page: https://patentgrep.com/patent/US8542755B2

## CPC

- H04B 1/40: Circuits
- H04B 1/0028: {wherein the AD/DA conversion occurs at baseband stage}
- H04B: TRANSMISSION

## Abstract

A communication system includes a RF subsystem that communicates with a BB subsystem through a digital RF-BB interface multiplexing I/Q data and control signals in both TX and RX directions. The RF subsystem includes a FIFO buffer in each respective TX and RX chain and a timer that assigns a timestamp to the continuous stream in both TX and RX chains whenever it is equal to a time event from the BB subsystem. The BB subsystem includes a sample counter that counts the number (k) of data samples at the FIFO buffer and a controller that defines the time event. Precise alignment at the air interface between a data burst from the RF subsystem and a data burst from the BB subsystem can be achieved using the timer, based on the relation between the timer value (n) and the sample count (k).

## Claims

### Claim 1

A communication system, comprising:
a Radio Frequency (RF) subsystem;
a Baseband (BB) subsystem; and
a digital interface operable to allow said radio frequency (RF) subsystem and said BB subsystem to communicate;
wherein said RF subsystem includes at least
a converter operable to convert a data burst into a continuous stream of data samples at a transmit (TX) chain and to convert a continuous stream into a data burst of data samples at a receive (RX) chain, respectively, and
a timer block operable to provide a timer value (n), assigning a time reference to said continuous stream of data samples, and to respond to a time event (TxStartValue, RxStartValue); and
wherein said BB subsystem includes at least
a controller operable to define said time event, and
a counter operable to count a number (k) of said data samples at said converter, said counter being aligned with said time reference based on a relation between said timer value (n) and said number (k); and
wherein the BB subsystem controller is operative to account for delays introduced by said digital interface by the relation between said timer value (n) and said number (k).

### Claim 2 (depends on 1)

The system according to claim 1 wherein said timer block comprises at least one comparator operable to compare said time event with said timer value (n) and to positively respond to said time event as a comparison result whenever said time event equals said timer value (n).

### Claim 3 (depends on 2)

The system according to claim 2, wherein said timer value (n) is an initial timer value (nRX0, nTX0) assigned as said time reference to the first data sample in a stream of samples at the receive (RX) chain and the transmit (TX) chain, respectively, which relate to first samples (kRX=0 and kTX=0) at the BB subsystem as soon as a first valid data sample amongst said continuous stream enters a reference point referred to by said timer block.

### Claim 4 (depends on 3)

The system according to claim 3, wherein said relation between said timer value (n) and said number (k) takes into consideration a delay parameter (τ) between said converter and said reference point, and a conversion parameter (p) for converting a count event into a time event.

### Claim 5 (depends on 4)

The system according to claim 4, wherein said relation between said timer value (n) and said number (k) further takes into consideration an offset parameter (Δ) between said converter and said reference point.

### Claim 6 (depends on 5)

The system according to claim 5, wherein said converter is a first-in first-out (FIFO) buffer.

### Claim 7 (depends on 2)

The system according to claim 2, wherein said timer block further comprises a counter operable to provide said timer value (n).

### Claim 8 (depends on 7)

The system according to claim 7, wherein said counter of said timer block and said at least one comparator are programmable.

### Claim 9

A method of generating a control process for controlling a radio frequency (RF) subsystem by a baseband (BB) subsystem over a digital interface, said method comprising:
initiating said control process in response to a time event (TxStartValue, RxStartValue) from said BB subsystem;
assigning a time reference by a timer block in said RF subsystem to a continuous stream of data samples towards and from said BB subsystem;
aligning a counter in said BB subsystem with said time reference based on a relation between a timer value (n) provided by said timer block and a number (k) of said data samples counted by said counter; and
controlling, by said BB subsystem, reception and transmission of said stream of data samples by said RF subsystem by providing said time reference across a digital interface between said BB subsystem and RF subsystem, such that delays introduced by said digital interface are accounted for by said time value (n) and number (k) relation.

### Claim 10 (depends on 9)

The method according to claim 9, further comprising comparing the time event with the timer value (n), and positively responding to the time event as a comparison result whenever the time event equals the timer value (n).

### Claim 11 (depends on 10)

The method according to claim 10, wherein the timer value (n) is an initial timer value (nRX0, nTX0) assigned as the time reference to the first data sample in a stream of samples at the receive (RX) chain and the transmit (TX) chain, respectively, which relate to first samples (kRX=0 and kTX=0) at the BB subsystem as soon as a first valid data sample amongst the continuous stream enters a reference point referred to by the timer block.

### Claim 12

A communication device for use in a wireless communication network, the device comprising:
a Radio Frequency (RF) unit operable to convert a data burst into a continuous stream of data samples at a transmit (TX) chain and to convert a continuous stream into a data burst of data samples at a receive (RX) chain, respectively;
a Baseband (BB) unit; and
a digital interface adapted to allow the RF unit and the BB unit to communicate;
wherein the BB unit comprises at least:
a controller operable to define a time event; and
a counter unit operable to count a number (k) of data samples at a converter in the RF unit, the counter unit aligned with a time reference of the continuous stream of data samples based on a relation between a timer value (n) maintained in the RF unit and the number (K), said relation accounting for delays introduced by said digital interface.

### Claim 13 (depends on 12)

The device according to claim 12, wherein the RF unit comprises:
a converter operable to convert a data burst into a continuous stream of data samples at a transmit (TX) chain and to convert a continuous stream into a data burst of data samples at a receive (RX) chain, respectively; and
a timer block operable to provide a timer value (n), assigning a time reference to the continuous stream of data samples, and to respond to a time event (TxStartValue, RxStartValue).

### Claim 14 (depends on 13)

The device according to claim 13, wherein the timer block is configured to compare the time event with the timer value (n), and to positively respond to the time event as a comparison result whenever the time event equals the timer value (n).

### Claim 15 (depends on 14)

The device according to claim 14, wherein the timer value (n) is an initial timer value (nRX0, nTX0) assigned as the time reference to the first data sample in a stream of samples at the receive (RX) chain and the transmit (TX) chain, respectively, which relate to first samples (kRx=0 and kTX=0) at the BB subsystem as soon as a first valid data sample amongst said continuous stream enters a reference point referred to by said timer block.

### Claim 16 (depends on 15)

The device according to claim 15, wherein the relation between the timer value (n) and the number (k) takes into consideration a delay parameter (τ) between the converter and the reference point, and a conversion parameter (ρ) for converting a count event into a time event.

### Claim 17 (depends on 16)

The device according to claim 16, wherein the relation between the timer value (n) and the number (k) further takes into consideration an offset parameter (Δ) between the converter and the reference point.

### Claim 18 (depends on 17)

The device according to claim 17, wherein the converter is a first-in first-out (FIFO) buffer.

### Claim 19 (depends on 14)

The device according to claim 14, wherein the timer block further comprises a counter operable to provide the timer value (n).

### Claim 20 (depends on 19)

The device according to claim 19, wherein the counter of the timer block and the at least one comparator are programmable.