# US 8,542,551 B2 · Circuit and method for reducing leakage current

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- Number: US 8,542,551 B2
- Document ID: US8542551B2
- Status: Granted
- Kind: B2
- Application number: 13/194,165
- Filed: 2011-07-29
- Published: 2013-01-31
- Granted: 2013-09-24
- Earliest claimed: 2011-07-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Dariusz Kowalczyk
- Inventors: Dariusz Kowalczyk
- Web page: https://patentgrep.com/patent/US8542551B2

## CPC

- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 7/00: Arrangements for writing information into, or reading information out from, a digital store (G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413)
- G11C 7/1069: {I/O lines read out arrangements}
- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C 11/4094: Bit-line management or control circuits
- H03K 17/693: Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00)
- G11C 2207/2227: Standby or low power modes
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A circuit comprises a first voltage source, a second voltage source, a first switch, firsts transistors, and a control circuitry. The first switch is configured to selectively couple the first voltage source or the second voltage source to a first signal line. The first transistors are in an IO circuitry and have first bulks configured to receive the first signal line. The control circuitry is configured to receive a clock and a command signal on a command signal line, and generate a first control signal on a first control signal line to control the first switch based on the clock and the command signal.

## Claims

### Claim 1

A circuit comprising:
a first voltage source and a second voltage source;
a first switching circuit configured to selectively couple the first voltage source or the second voltage source to a first signal line;
first transistors in an IO circuitry having first bulks configured to receive the first signal line; and
a control circuitry configured to receive a clock and a command signal on a command signal line and generate a first control signal on a first control signal line to control the first switching circuit based on the clock and the command signal.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein
the circuit operates in at least a first mode and a second mode based on the clock and logic levels of the command signal;
the first switching circuit is configured to couple the first voltage source to the first signal line when the circuit operates in the first mode; and
the first switching circuit is configured to couple the second voltage source to the first signal line when the circuit operates in the second mode.

### Claim 3 (depends on 2)

The circuit of claim 2, wherein the circuit is configured to operate in at least one of a third mode and a fourth mode, and the first switching circuit is configured to couple the second voltage source to the first signal line when the circuit operates in the third mode or the fourth mode.

### Claim 4 (depends on 2)

The circuit of claim 2, wherein
the circuit is configured to enter the first mode when the command signal line has a first command logic level and a first edge of the clock has a first transition since the command signal line having the first command logic level; and
the circuit is configured to enter the second mode when the command signal line has a second command logic level and a second edge of the clock has a first transition since the command having the second command logic level.

### Claim 5 (depends on 1)

The circuit of claim 1, further comprising:
a third voltage source and a fourth voltage source;
a second switching circuit configured to selectively couple the third voltage source or the fourth voltage source to a second signal line; and
second transistors in the IO circuitry having second bulks configured to receive the second signal line.

### Claim 6 (depends on 5)

The circuit of claim 5 further comprising a sub-circuit configured to generate a second control signal from the first control signal, the first control signal line configured to control the first switching circuit and the second control signal line configured to control the second switching circuit.

### Claim 7 (depends on 1)

The circuit of claim 1, wherein
the first voltage source is configured to provide an operational voltage and the second voltage source is configured to provide a first voltage higher than the operational voltage; or
the first voltage source is configured to provide a reference voltage and the second voltage source is configured to provide a second voltage lower than the reference voltage.

### Claim 8

A method for reducing leakage current in a memory macro, comprising:
changing from a first operational mode to a second operational mode of the memory macro;
changing a first voltage value at first bulks of transistors of an input/output circuitry of the memory macro to a second voltage value; and
maintaining the first voltage value at bulks of transistors of a memory circuitry of the memory macro,
wherein
the IO circuitry carries first data for a write operation to memory cells in the memory circuitry and second data for a read operation from the memory cells in the memory circuitry; and
the first operational mode includes at least one of the read operation and the write operation, and the second operational mode prohibits the read operation and the write operation.

### Claim 9 (depends on 8)

The method of claim 8, wherein changing from the first operational mode to the second operational mode comprises:
causing a command signal to transition from a first command logic value to a second command logic value; and
entering the second operational mode when a clock signal first transitions from a first clock logic value to a second clock logic value since the command signal has the second command logic value.

### Claim 10 (depends on 8)

The method of claim 8, wherein changing the first voltage value at the bulks of the transistors of the IO circuitry comprises raising the first voltage value if the transistors of the IO circuitry are PMOS transistors, and/or lowering the first voltage value if the transistors of the IO circuitry are NMOS transistors.

### Claim 11 (depends on 8)

The method of claim 8 further comprising:
changing from the second operational mode to the first operational mode; and
changing the second voltage value at the bulks of the transistors of the IO circuitry to the first voltage value.

### Claim 12 (depends on 11)

The method of claim 11, wherein changing from the second operational mode to the first operational mode comprises:
causing a command signal to transition from a first command logic value to a second command logic value; and
entering the first operational mode when a clock signal first transitions from a first clock logic value to a second clock logic value since the command signal has the second command logic value.

### Claim 13 (depends on 8)

The method of claim 8, further comprising refreshing memory cells in the memory circuitry while the memory macro operates in the second operational mode.

### Claim 14 (depends on 8)

The method of claim 8, wherein changing the first voltage value at the bulks of the transistors of the IO circuitry of the memory macro to the second voltage value comprising switching a first voltage source to a second voltage source to the bulks of the transistors.

### Claim 15 (depends on 8)

The method of claim 8, wherein, when the memory macro is in the second operational mode, at least one of the following conditions is met:
there is no switching activity in the IO circuitry;
the clock is cut off;
a data refresh is stopped;
internal power supplies are disabled; and
an operational voltage is cut off.

### Claim 16

A memory circuit comprising:
a first voltage source and a second voltage source;
a first switching circuit configured to selectively couple the first voltage source or the second voltage source to a first signal line;
first transistors in an IO circuitry having first bulks configured to receive the first signal line,
wherein
the circuit is configured to operate in a first operational mode and in at least one of a second operational mode, a third operational mode or a fourth operational mode;
in the first operational mode, the circuit is configured to have a read operation or a write operation, and the first switching circuit is configured to electrically couple the first voltage source to the first signal line, the first bulks thereby having a first voltage value from the first voltage source;
in the second, the third, or the fourth operational mode, the first switching circuit is configured to electrically couple the second voltage source to the first signal line, the first bulks thereby having a second voltage value from the second voltage source.

### Claim 17 (depends on 16)

The memory circuit of claim 16, further comprising:
a third voltage source and a fourth voltage source;
a second switching circuit configured to selectively couple the third voltage source or the fourth voltage source to a second signal line; and
second transistors in the IO circuitry having second bulks configured to receive the second signal line.

### Claim 18 (depends on 17)

The memory circuit of claim 17 further comprising a sub-circuit configured to generate a second control signal from a first control signal, the first control signal line configured to control the first switching circuit and the second control signal line configured to control the second switching circuit.

### Claim 19 (depends on 16)

The memory circuit of claim 16, wherein
the memory circuit is configured to enter the first mode when a command signal line has a first command logic value and a first edge of the clock has a first transition since the command signal line having the first command logic value; and
the memory circuit is configured to enter the second mode when the command signal line has a second command logic value and a second edge of the clock has a first transition since the command having the second command logic value.

### Claim 20 (depends on 16)

The memory circuit of claim 16, wherein
the first voltage source is configured to provide an operational voltage and the second voltage source is configured to provide a first voltage higher than the operational voltage; or
the first voltage source is configured to provide a reference voltage and the second voltage source is configured to provide a second voltage lower than the reference voltage.