# US 8,542,548 B2 · Semiconductor memory device and thermal code output circuit capable of correctly measuring thermal codes > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,542,548 B2 - Document ID: US8542548B2 - Status: Granted - Kind: B2 - Application number: 12/228,819 - Filed: 2008-08-15 - Published: 2009-10-29 - Granted: 2013-09-24 - Earliest claimed: 2008-04-28 - Assignees: Hynix Semiconductor Inc. - Applicants: Sun Mo An - Inventors: Sun Mo An - Web page: https://patentgrep.com/patent/US8542548B2 ## CPC - G11C 7/1051: {Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits} - G11C 5/143: {Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels (G11C5/148 takes precedence); Switching between alternative supplies (G11C5/141 takes precedence)} - G11C 7/04: with means for avoiding disturbances due to temperature effects - G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals} - G11C 29/02: Detection or location of defective auxiliary circuits, e.g. defective refresh counters - G11C 11/401: forming cells needing refreshing or charge regeneration, i.e. dynamic cells - G11C 2029/5002: {Characteristic} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A thermal code output circuit is provided, comprising a pulse signal generator configured to receive multiple period signals and generate a pulse signal in response to a test mode signal, a thermal code output unit configured to output multiple thermal codes in response to the pulse signal, and a strobing signal output unit configured to output the pulse signal or a reference voltage selectively as a strobing signal in response to the test mode signal. ## Claims ### Claim 1 A thermal code output circuit, comprising: a pulse signal generator configured to generate an enable signal and an end signal in response to a test mode signal and multiple period signals and generate a pulse signal in response to the enable signal when the end signal is disabled; a thermal code output unit configured to receive multiple thermal codes from a thermal sensor, and output the multiple thermal codes in synchronization with the pulse signal; and a strobing signal output unit configured to output the pulse signal or a reference voltage selectively as a strobing signal in response to the test mode signal. ### Claim 2 (depends on 1) The thermal code output circuit of claim 1, further comprising a period signal generator configured to increase a period of a period signal inputted through a counting operation and generate the multiple period signals. ### Claim 3 (depends on 1) The thermal code output circuit of claim 1, wherein the pulse signal generator includes: an enable generator configured to receive a first period signal and the test mode signal and generate the enable signal; an end signal generator configured to receive the first period signal and second through fourth period signals and generate the end signal; and a signal generator configured to receive the enable signal and the end signal and generate the pulse signal. ### Claim 4 (depends on 3) The thermal code output circuit of claim 3, wherein the enable signal is generated as a period signal having a same period as the first period signal during the test mode signal is enabled. ### Claim 5 (depends on 3) The thermal code output circuit of claim 3, wherein the end signal generator generates the end signal in which an enable interval is adjusted according to a combination of the first through fourth period signals. ### Claim 6 (depends on 3) The thermal code output circuit of claim 3, wherein the signal generator generates the pulse signal having a predetermined pulse width from an interval that the enable signal is enabled to an interval that the end signal is enabled, and the pulse signal is generated with a same period as the first period signal. ### Claim 7 (depends on 3) The thermal code output circuit of claim 3, wherein the signal generator includes: a delay unit configured to delay the enable signal for a predetermined interval; an inverter configured to invert the enable signal; a first logic element configured to receive an output signal of the delay unit and an output signal of the inverter and perform a logic operation; and a second logic element configured to receive an inverting signal of the end signal and an output signal of the first logic element and perform a logic operation. ### Claim 8 (depends on 1) The thermal code output circuit of claim 1, wherein the thermal code output unit sequentially outputs multiple thermal codes through a pad in response to the pulse signal. ### Claim 9 (depends on 1) The thermal code output circuit of claim 1, wherein the strobing signal output unit includes: a first transmission gate configured to transmit the reference voltage to a pad in response to the test mode signal; and a second transmission gate configured to transmit the pulse signal to the pad in response to the test mode signal. ### Claim 10 (depends on 1) The thermal code output circuit of claim 1, wherein the reference voltage has a level corresponding to the internal temperature of a semiconductor memory device. ### Claim 11 (depends on 1) The thermal code output circuit of claim 1, wherein the multiple thermal codes are outputted in synchronization with the strobing signal. ### Claim 12 A semiconductor memory device, comprising: a thermal sensor configured to generate a thermal code; a thermal code output unit configured to generate an enable signal and an end signal in response to a test mode signal and multiple period signals, generate a pulse signal in response to the enable signal when the end signal is disabled, receive multiple thermal codes from a thermal sensor, and output the multiple thermal codes in synchronization with the pulse signal; a first pad configured to output the thermal code; and a second pad configured to output the pulse signal as a strobing signal. ### Claim 13 (depends on 12) A semiconductor memory device of claim 12, wherein the thermal code output unit includes: a pulse signal generator configured to generate the enable signal and the end signal in response to the test mode signal and the multiple period signals, and generate the pulse signal in response to the enable signal when the end signal is disabled; a thermal code output unit configured to output multiple thermal codes in response to the pulse signal; and a strobing signal output unit configured to output the pulse signal or a reference voltage selectively as a strobing signal in response to the test mode signal. ### Claim 14 (depends on 13) The semiconductor memory device of claim 13, wherein the thermal code output unit further comprises a period signal generator configured to increase a period of a period signal inputted through a counting operation and generate the multiple period signals. ### Claim 15 (depends on 13) The semiconductor memory device of claim 13, wherein the pulse signal generator includes: an enable generator configured to receive a first period signal and the test mode signal and generate the enable signal; an end signal generator configured to receive the first period signal and second through fourth period signals and generate the end signal; and a signal generator configured to receive the enable signal and the end signal and generate the pulse signal. ### Claim 16 (depends on 15) The semiconductor memory device of claim 15, wherein the enable signal has a same period as the first period signal during the test mode signal is enabled. ### Claim 17 (depends on 16) The semiconductor memory device of claim 16, wherein the end signal generator generates the end signal in which an enable interval is adjusted according to a combination of the first through fourth period signals. ### Claim 18 (depends on 15) The semiconductor memory device of claim 15, wherein the signal generator generates the pulse signal having a predetermined pulse width from an interval that the enable signal is enabled to an interval that the end signal is enabled, and the pulse signal is generated with a same period as the first period signal. ### Claim 19 (depends on 15) The semiconductor memory device of claim 15, wherein the signal generator includes: a delay unit configured to delay the enable signal for a predetermined interval; an inverter configured to invert the enable signal; a first logic element configured to receive an output signal of the delay unit and an output signal of the inverter and perform a logic operation; and a second logic element configured to receive an inverting signal of the end signal and an output signal of the first logic element and perform a logic operation. ### Claim 20 (depends on 13) The semiconductor memory device of claim 13, wherein the thermal code output unit sequentially outputs multiple thermal codes through the first pad in response to the pulse signal. ### Claim 21 (depends on 13) The semiconductor memory device of claim 13, wherein the strobing signal output unit includes: a first transmission gate configured to transmit the reference voltage to the second pad in response to the test mode signal; and a second transmission gate configured to transmit the pulse signal to the second pad in response to the test mode signal. ### Claim 22 (depends on 13) The semiconductor memory device of claim 13, wherein the reference voltage has a level corresponding to the internal temperature of a semiconductor memory device. ### Claim 23 (depends on 13) The semiconductor memory device of claim 13, wherein the multiple thermal codes are outputted in synchronization with the strobing signal.