# US 8,542,545 B2 · Repairing soft failures in memory cells in SRAM arrays

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,542,545 B2
- Document ID: US8542545B2
- Status: Granted
- Kind: B2
- Application number: 13/070,799
- Filed: 2011-03-24
- Published: 2012-09-27
- Granted: 2013-09-24
- Earliest claimed: 2011-03-24
- Assignees: Texas Instruments Incorporated
- Applicants: Wah Kit Loh; Beena Pious
- Inventors: Wah Kit Loh; Beena Pious
- Web page: https://patentgrep.com/patent/US8542545B2

## CPC

- G11C 11/417: for memory cells of the field-effect type
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 11/412: using field-effect transistors only
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An embodiment of the invention provides a method of repairing soft failures in memory cells of an SRAM array. The SRAM array is tested to determine the location and type of soft failures in the memory cells. An assist circuit is activated that changes a voltage in a group of memory cells with the same type of soft failure. The change in voltage created by the assist circuit repairs the soft failures in the group. The group may be a word line or a bit line. The type of soft failures includes a failure during a read of a memory cell and a failure during the write of a memory cell.

## Claims

### Claim 1

A method of repairing soft failures in memory cells of an SRAM array comprising:
testing the SRAM array to determine locations where the memory cells have soft failures;
testing the SRAM array to determine types of soft failures in the memory cells with soft failures;
activating at least one assist circuit;
wherein the at least one assist circuit changes a voltage in the memory cells with soft failures that have one and only one type of soft failure;
wherein the changed voltage is used during normal operation of the SRAM array;
wherein the memory cells with soft failures that have one and only one type of soft failure are contained in a group.

### Claim 2 (depends on 1)

The method of claim 1 wherein a type of soft failure is a write failure.

### Claim 3 (depends on 2)

The method of claim 2 wherein the write failure occurs while attempting to write a logical one to the memory cells.

### Claim 4 (depends on 3)

The method of claim 3 wherein the group is a word line.

### Claim 5 (depends on 4)

The method of claim 4 wherein a voltage on the word line is increased with respect to VDD of the memory cells during writing of the memory cells.

### Claim 6 (depends on 3)

The method of claim 3 wherein the group is bit line pair.

### Claim 7 (depends on 6)

The method of claim 6 wherein a voltage on VDD of the memory cells is decreased with respect to a voltage of a word line of the memory cells.

### Claim 8 (depends on 6)

The method of claim 6 wherein a voltage on a bit line from the bit line pair is decreased with respect to VSS of the memory cells.

### Claim 9 (depends on 1)

The method of claim 1 wherein the type of soft failure is a read failure.

### Claim 10 (depends on 9)

The method of claim 9 wherein the read failure occurs while attempting to read a logical zero from the memory cells.

### Claim 11 (depends on 10)

The method of claim 10 wherein the group is bit line pair.

### Claim 12 (depends on 11)

The method of claim 11 wherein VDD of the memory is increased with respect to a voltage on the word line of the memory cells during reading of the memory cells.

### Claim 13 (depends on 12)

The method of claim 12 wherein VDD of the memory is increased with respect to a voltage on the word line of the memory cells during reading of the memory cells using capacitive coupling.

### Claim 14 (depends on 10)

The method of claim 10 wherein the group is a word line.

### Claim 15 (depends on 14)

The method of claim 14 wherein a voltage on the word line is decreased with respect to VDD of the memory cells during reading of the memory cells.

### Claim 16

A method of repairing bit failures in memory cells of an SRAM array comprising:
testing the SRAM array to determine locations of the memory cells with hard bit failures;
replacing the memory cells with hard bit failures with redundant memory cells;
testing the SRAM array to determine locations of the memory cells with soft failures;
testing the SRAM array to determine types of soft failure in the memory cells with soft failures;
activating an assist circuit;
wherein the assist circuit changes a voltage in the memory cells with soft failures that have one and only one type of soft failure;
wherein the changed voltage is used during normal operation of the SRAM array;
wherein the memory cells with soft failures that have one and only one type of soft failure are contained in a group.

### Claim 17 (depends on 16)

The method of claim 16 wherein the SRAM array is on a stand-alone SRAM memory integrated circuit.

### Claim 18 (depends on 16)

The method of claim 16 wherein the SRAM array is part of an SRAM wherein the SRAM is included on a system on a chip (SOC).

### Claim 19 (depends on 16)

The method of claim 16 wherein replacing the memory cells with hard bit failures with redundant memory cells includes blowing fuses.

### Claim 20 (depends on 16)

The method of claim 16 wherein activating an assist circuit includes electrically selecting the assist circuit.