# US 8,542,544 B2 · Semiconductor device having a plurality of memory regions and method of testing the same

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- Number: US 8,542,544 B2
- Document ID: US8542544B2
- Status: Granted
- Kind: B2
- Application number: 12/926,889
- Filed: 2010-12-15
- Published: 2012-02-02
- Granted: 2013-09-24
- Earliest claimed: 2010-07-28
- Assignees: Elpida Memory, Inc.
- Applicants: Katsuyoshi Komatsu; Koji Mine
- Inventors: Katsuyoshi Komatsu; Koji Mine
- Web page: https://patentgrep.com/patent/US8542544B2

## CPC

- G11C 29/24: Accessing extra cells, e.g. dummy cells or redundant cells
- G11C 29/70: {Masking faults in memories by using spares or by reconfiguring}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A semiconductor device may include, but is not limited to, first and second memory regions, and first to fifth control circuits. The first and second memory regions are mutually exclusive at the same time. The first control circuit performs a first access to the first memory region. The second control circuit performs a second access to the second memory region. The third control circuit controls activation and deactivation of the first and second control circuits based on a first logic received from a plurality of first external terminals. The fourth control circuit switches between the first and second accesses based on at least a second logic received from a second external terminal. The fifth control circuit controls validation and invalidation of the fourth control circuit.

## Claims

### Claim 1

A semiconductor device comprising:
a first memory region;
a second memory region, the first and second memory regions being mutually exclusive at the same time;
a first control circuit that performs a first access to the first memory region;
a second control circuit that performs a second access to the second memory region;
a third control circuit that controls activation and deactivation of the first and second control circuits based on a first logic received from a plurality of first external terminals;
a fourth control circuit that switches between the first and second accesses based on at least a second logic received from a second external terminal; and
a fifth control circuit that controls validation and invalidation of the fourth control circuit.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, further comprising:
the fifth control circuit that controls the validation based on a third logic indicated by a test mode command, the test mode command ordering the semiconductor device to enter a test operation mode.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein
the fifth control circuit generates a first signal that validates an operation of the fourth control circuit based on the third logic, and
the fourth circuit switches between the first and second accesses based on the second logic and the first signal.

### Claim 4 (depends on 2)

The semiconductor device according to claim 2, wherein the test mode command is a mode register command supplied from the plurality of first external terminals.

### Claim 5 (depends on 2)

The semiconductor device according to claim 2, wherein the second external terminal is different from the plurality of first external terminals.

### Claim 6 (depends on 2)

The semiconductor device according to claim 2, wherein the test mode command is supplied from at least a third external terminal that is different from the plurality of first external terminals.

### Claim 7 (depends on 3)

The semiconductor device according to claim 3, wherein the third control circuit activates the second logic.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein
the first and second memory regions comprise a plurality of memory cells defined by a plurality of rows and a plurality of columns,
the first control circuit comprises a first circuit that selects a first column of the plurality of columns, and the first column being included in the first memory region, and
the second control circuit comprises a second circuit that selects a second column of the plurality of columns if a defective memory cell of the plurality of memory cells is connected to the first column, the second column being included in the second memory region.

### Claim 9 (depends on 8)

The semiconductor device according to claim 8, further comprising:
a third circuit that selects one of the plurality of rows, and
wherein the third control circuit controls the third circuit to activate the first and second control circuits and controls the third circuit to select the one of the plurality of rows when an active command is supplied to the plurality of first external terminals, the active command ordering selection of one of the plurality of rows.

### Claim 10 (depends on 9)

The semiconductor device according to claim 9, wherein
any one of a write command and a read command is supplied to the plurality of first external terminals after the active command is supplied, the write command ordering writing of data in the first memory region, and the read command ordering reading of data from the first memory region, and
the fourth control circuit allows, based on the write command or the read command, any one of the first and second circuits to operate.

### Claim 11 (depends on 9)

The semiconductor device according to claim 9, wherein data is read from or written in one of the plurality of memory cells which is accessed based on the one of the plurality of rows and any one of the first and second columns.

### Claim 12

A method of testing a semiconductor device, comprising:
supplying a first logic to a mode register one time;
supplying a first command to a command control circuit one time, the first command ordering activation of a word line;
supplying a second command and address information to the command control circuit multiple times, the second command ordering selection of a bit line based on the address information;
supplying a second logic to a test circuit simultaneously with the second command, the second logic ordering selection of any one of the bit line and a redundant bit line correlated to the bit line; and
performing data access corresponding to the bit line and the redundant bit line based on the first and second logics without supplying a third command that orders deactivation of the word line.

### Claim 13 (depends on 12)

The method according to claim 12, wherein the second logic is changed based on each of the plurality of second commands.

### Claim 14 (depends on 13)

The method according to claim 13, wherein
the first and second commands are supplied from a plurality of first external terminals, and
the second logic is supplied from a second external terminal that is different from the plurality of first external terminals.

### Claim 15 (depends on 14)

The method according to claim 14, wherein the first logic is supplied to the mode register by supplying a mode resister command.

### Claim 16 (depends on 15)

The method according to claim 15, wherein the mode resister command is supplied from the plurality of first external terminals.

### Claim 17 (depends on 14)

The method according to claim 14, wherein the first logic is supplied from at least a third external terminal that is different from the plurality of first external terminals.