# US 8,542,540 B2 · Nonvolatile memory and methods for manufacturing the same with molecule-engineered tunneling barriers

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- Number: US 8,542,540 B2
- Document ID: US8542540B2
- Status: Granted
- Kind: B2
- Application number: 12/748,253
- Filed: 2010-03-26
- Published: 2010-09-30
- Granted: 2013-09-24
- Earliest claimed: 2009-03-27
- Assignees: Cornell University
- Applicants: Edwin C. Kan; Tuo-Hung Hou
- Inventors: Edwin C. Kan; Tuo-Hung Hou
- Web page: https://patentgrep.com/patent/US8542540B2

## CPC

- H10B 43/30: characterised by the memory core region
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10B 41/30: characterised by the memory core region
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/037: {comprising charge-trapping insulators}
- G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)}
- H10B: ELECTRONIC MEMORY DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Embodiments of tunneling barriers and methods for same can embed modules exhibiting a monodispersion characteristic into a dielectric layer (e.g., between first and second layers forming a dielectric layer). In one embodiment, by embedding C60 molecules inbetween first and second insulating layers forming a dielectric layer, a field sensitive tunneling barrier can be implemented. In one embodiment, the tunneling barrier can be between a floating gate and a channel in a semiconductor structure. In one embodiment, a tunneling film can be used in nonvolatile memory applications where C60 provides accessible energy levels to prompt resonant tunneling through the dielectric layer upon voltage application.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor substrate; and
a nonvolatile memory cell provided on the semiconductor substrate, the nonvolatile memory cell comprising:
a tunnel insulating film provided over a surface of the semiconductor substrate, the tunnel insulating film comprising a layer of monodispersed molecules;
a charge storage layer provided on the tunnel insulating film;
an insulating film provided on the charge storage layer; and
a conductive layer provided on the insulating film.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein said monodispersed molecules include fullerene molecules.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the fullerene molecules comprise C60 molecules.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein C60 molecules include variable prescribed energy level characteristics by chemical functionalization.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein said monodispersed molecules are conductive, and wherein the monodispersed molecules comprise C60 molecules and a metal molecule, wherein the metal molecule comprises chromium or titanium.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the layer of monodispersed molecules are between first and second tunnel insulating layers.

### Claim 7 (depends on 6)

The semiconductor device according to claim 6, wherein the first and second tunnel insulating layers or the insulating film comprise a silicon oxide film or a dielectric insulating film.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the layer of monodispersed molecules is about 0.5 nm thick, less than 1 nm thick, less than 1.2 nm thick, less than 2 nm thick, or less than 3 nm thick, and wherein the first and second tunnel insulating layers are less than 8 nm thick, less than 5 nm thick, less than 3 nm thick, less than 2 nm thick, or less than 1 nm thick.

### Claim 9 (depends on 1)

The semiconductor device of claim 1 comprising:
a first electrode coupled to a first impurity region in the semiconductor substrate;
a second impurity region in the semiconductor substrate; and
an electrode coupled to a channel region in the semiconductor substrate between the first impurity region and the second impurity region, wherein the tunnel insulating film is over a portion of the channel region.

### Claim 10 (depends on 9)

The semiconductor device according to claim 9, wherein the conductive layer is a control electrode, the first electrode is a source electrode and the second electrode is a drain electrode, wherein the first and second impurity regions comprise an n-type impurity or a p-type impurity.

### Claim 11 (depends on 1)

The semiconductor device according to claim 1, wherein the nonvolatile memory cell stores more than one bit of data.

### Claim 12 (depends on 1)

The semiconductor device according to claim 1, wherein the semiconductor device comprises an array of memory cells, wherein the nonvolatile memory cell is a NAND type nonvolatile memory cell, or a NOR type nonvolatile memory cell.

### Claim 13 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor device comprises a flash memory card, an EEPROM device, or a nonvolatile memory device.

### Claim 14

A nonvolatile flash memory card, comprising:
a random access memory array;
an input/output unit to operatively connect the random access memory to receive or transmit data; and
a microcontroller to control data storage or data retrieval between the input/output unit and the random access memory array, wherein at least one cell of the random access memory array comprises,
a semiconductor region having a source region, a drain region, and a channel region provided between the source region and the drain region,
a first tunnel insulation film formed on the channel region,
a barrier layer formed on the first tunnel insulation film, the barrier layer comprising a layer of monodispersed molecules, the barrier layer including a prescribed energy barrier level,
a second tunnel insulation film formed on the barrier layer,
a charge storage portion formed over the second tunnel insulation film, and
a control electrode on the charge storage portion.

### Claim 15 (depends on 14)

The nonvolatile flash memory card of claim 14, wherein said barrier layer is monodispersed molecules are-fullerene molecules.

### Claim 16 (depends on 15)

The nonvolatile flash memory card of claim 15, wherein the fullerene molecules comprise C60 molecules.

### Claim 17 (depends on 14)

The nonvolatile flash memory card of claim 14, wherein said monodispersed molecules are conductive.