# US 8,542,538 B2 · Semiconductor memory device which stores plural data in a cell

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- Number: US 8,542,538 B2
- Document ID: US8542538B2
- Status: Granted
- Kind: B2
- Application number: 13/754,057
- Filed: 2013-01-30
- Published: 2013-06-13
- Granted: 2013-09-24
- Earliest claimed: 2004-01-30
- Assignees: Kabushiki Kaisha Toshiba
- Applicants: Kabushiki Kaisha Toshiba
- Inventors: Noboru Shibata; Tomoharu Tanaka
- Web page: https://patentgrep.com/patent/US8542538B2

## CPC

- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/10: Programming or data input circuits
- G11C 16/12: Programming voltage switching circuits
- G11C 16/3454: {Arrangements for verifying correct programming or for detecting overprogrammed cells}
- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- G11C 2211/5621: Multilevel programming verification
- G11C 2211/5648: Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.

## Claims

### Claim 1

A semiconductor memory device comprising:
a memory cell array configured to have a plurality of memory cells arranged in a matrix, each of said plurality of memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3); and
a control circuit which controls the potentials of the word line and bit line according to input data and writes data into a memory cell,
wherein the control circuit writes data into the memory cell to an a1-valued (a1≦n) threshold voltage in a first write operation, to an a2-valued (a2≦n) threshold voltage in a second write operation, and to an ak-valued (ak≦n) threshold voltage in a k-th write operation (k is a natural number equal to or larger than 2: k≦n), in the first to k-th write operations, raises a program voltage in increments of ΔVpgm, and carries out write operations by repeating a program and verify operation, ΔVpgm in the first to k-th write operations fulfilling the following expression: ΔVpgm in the first write operation>ΔVpgm in the second write operation> . . . >ΔVpgm in the kth write operation.

### Claim 2 (depends on 1)

The semiconductor memory device according to claim 1, wherein the memory cells constitute a NAND flash memory.