# US 8,542,537 B2 · Method and apparatus for temperature compensation for programming and erase distributions in a flash memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,542,537 B2 - Document ID: US8542537B2 - Status: Granted - Kind: B2 - Application number: 13/098,378 - Filed: 2011-04-29 - Published: 2012-11-01 - Granted: 2013-09-24 - Earliest claimed: 2011-04-29 - Assignees: Spansion LLC - Applicants: Allan Parker - Inventors: Allan Parker - Web page: https://patentgrep.com/patent/US8542537B2 ## CPC - G11C 16/10: Programming or data input circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A method and apparatus for a memory device is provided. The memory device includes a memory cell, a memory controller, and a temperature-sensing device that detects a temperature. The memory controller enables adjusting, based on the detected temperature, a parameter associated with a bit-altering operation to the memory cell that changes a threshold voltage of the memory cell such that the threshold voltage to which the memory cell is changed to by the bit-altering operation is compensated for variations in temperature. ## Claims ### Claim 1 A memory device, comprising: a temperature-sensing device that is arranged to detect a temperature; a memory cell; and a memory controller that is configured to enable adjusting, based on the detected temperature, a parameter associated with a bit-altering operation of the memory cell that changes a threshold voltage of the memory cell such that the threshold voltage to which the memory cell is changed to by the bit-altering operation is substantially compensated for variations in temperature. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the bit-altering operation includes at least one of a program operation or an erase operation. ### Claim 3 (depends on 1) The memory device of claim 1, wherein the parameter associated with the bit-altering operation is a pulse duration for which a voltage is applied to the memory cell. ### Claim 4 (depends on 1) The memory device of claim 1, wherein the memory controller is configured to adjust the parameter based on a stored scaling factor correlating changes in temperature to changes in the parameter. ### Claim 5 (depends on 1) The memory device of claim 1, wherein the temperature-sensing device includes means for temperature sensing; or the memory cell includes means for storing information; or the memory controller includes means for enabling adjusting, based on the detected temperature, the parameter associated with the bit-altering operation of a memory cell of the plurality of memory cells that changes the threshold voltage of the memory cell such that the threshold voltage to which the memory cell is changed to by the bit-altering operation is substantially compensated for variations in temperature. ### Claim 6 (depends on 1) A machine-readable storage medium that includes an electronic design file that is configured to control a fabrication of the memory device of claim 1. ### Claim 7 (depends on 1) A method, comprising transmitting, over a network, an article of manufacture including a machine-readable medium that includes an electronic design file that is configured to control a fabrication of the memory device of claim 1. ### Claim 8 (depends on 1) The memory device of claim 1, wherein the temperature-sensing device is a temperature-sensing diode. ### Claim 9 (depends on 8) The memory device of claim 8, wherein the memory controller is configured to convert a voltage across the temperature-sensing diode into the detected temperature. ### Claim 10 (depends on 1) The memory device of claim 1, wherein the memory cell has a drain, and wherein the parameter associated with the bit-altering operation is a bit line voltage that is provided to the drain of the memory cell during the bit-altering operation. ### Claim 11 (depends on 10) The memory device of claim 10, farther comprising: a charge pump that is arranged to provide a first boosted voltage; and a voltage regulator that is arranged to receive the first boosted voltage, and to provide the bit line voltage, wherein the voltage regulator is arranged to regulate the bit line voltage to a voltage level that is based on control from the memory controller. ### Claim 12 (depends on 1) The memory device of claim 1, wherein the memory cell has a control gate, and wherein the parameter associated with the bit-altering operation is a word line voltage that is provided to the control gate of the memory cell during the bit-altering operation. ### Claim 13 (depends on 12) The memory device of claim 12, further comprising: a charge pump that is arranged to provide a first boosted voltage; and a voltage regulator that is arranged to receive the first boosted voltage, and to provide the word line voltage, wherein the voltage regulator is arranged to regulate the word line voltage to a voltage level that is based on control from the memory controller. ### Claim 14 A method, comprising: detecting a temperature; and adjusting, based on the detected temperature, a parameter associated with a bit-altering operation of a memory cell that changes a threshold voltage of the memory cell such that the threshold voltage to which the memory cell is changed to by the bit-altering operation is substantially compensated for variations in temperature. ### Claim 15 (depends on 14) The method of claim 14, wherein the bit-altering operation includes at least one of a program operation or an erase operation. ### Claim 16 (depends on 14) The method of claim 14, wherein the memory cell has a drain, and wherein the parameter associated with the bit-altering operation is a bit line voltage that is provided to the drain of the memory cell during the bit-altering operation. ### Claim 17 (depends on 14) The method of claim 14, wherein the memory cell has a control gate, and wherein the parameter associated with the bit-altering operation is a word line voltage that is provided to the control gate of the memory cell during the bit-altering operation. ### Claim 18 (depends on 14) The method of claim 14, wherein the parameter associated with the bit-altering operation is a pulse duration for which a voltage is applied to the memory cell. ### Claim 19 (depends on 14) The method of claim 14, wherein the memory controller is configured to adjust the parameter based on a stored scaling factor correlating changes in temperature to changes in the parameter. ### Claim 20 (depends on 14) The method of claim 14, wherein detecting the temperature includes: converting a voltage across a temperature-sensing diode into the detected temperature.