# US 8,542,532 B2 · Memory access method and flash memory using the same

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- Number: US 8,542,532 B2
- Document ID: US8542532B2
- Status: Granted
- Kind: B2
- Application number: 13/298,443
- Filed: 2011-11-17
- Published: 2013-05-23
- Granted: 2013-09-24
- Earliest claimed: 2011-11-17
- Assignees: Macronix International Co., Ltd.
- Applicants: Chung-Kuang Chen; Shuo-Nan Hung; Chun-Hsiung Hung
- Inventors: Chung-Kuang Chen; Shuo-Nan Hung; Chun-Hsiung Hung
- Web page: https://patentgrep.com/patent/US8542532B2

## CPC

- G11C 16/04: using variable threshold transistors, e.g. FAMOS
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/06: Auxiliary circuits, e.g. for writing into memory
- G11C 16/32: Timing circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory access method is applied in a memory controller for accessing an NAND memory array, including a number of respective select switches globally controlled with a string select signal. The memory access method includes the following steps. A stream bias signal and a selected word line signal are respectively provided on a selected stream and on a selected cell of the selected stream, and the rest of memory cells are turned on as pass transistors, in the setup phase. A discharge path is provided to eliminate coupling charge presented on unselected streams, in the setup phase. Then, the string select signal is enabled to have the selected stream connected to a sense unit via a metal bit line and according read the selected cell in a voltage sensing scheme, in a read phase, which does not overlap with the setup phase.

## Claims

### Claim 1

A memory access method, applied in a memory controller for accessing an NAND memory array, in which memory cells are arranged into a plurality of streams, which are globally controlled with a string select signal, the memory access method comprising:
providing a stream bias signal on a selected stream among the plurality of streams and providing a selected word line signal on a selected cell of the selected stream, in a setup phase;
providing a plurality of unselected word line signals on the rest of memory cells, to have the rest of memory cells turned on as pass transistors, in the setup phase;
providing a discharge path connected to the plurality of streams to accordingly eliminate coupling charge presented on at least an unselected stream among the plurality of streams, in the setup phase; and
enabling the string select signal to have the selected stream connected to a sense unit via a metal bit line and according read the selected cell in a voltage sensing scheme, in a read phase, which does not overlap with the setup phase.

### Claim 2 (depends on 1)

The memory access method according to claim 1, wherein step of providing the discharge path further comprises:
enabling the string select signal to have the plurality of streams globally connected to the metal bit line and have the at least an unselected stream discharged via the metal bit line.

### Claim 3 (depends on 1)

The memory access method according to claim 1, further comprising:
determining a first sub-phase within the setup phase, wherein,
the step of providing the stream bias signal and the selected word line signal and the step of providing the plurality of unselected word line signals are both executed in the first sub-phase.

### Claim 4 (depends on 3)

The memory access method according to claim 3, further comprising:
determining a second sub-phase within the setup phase, wherein,
the step of providing the discharge path is executed in the second sub-phase.

### Claim 5

A flash memory, comprising:
a sense unit;
an NAND memory array, comprising a plurality of memory cells, wherein the memory cells are arranged into a plurality of streams, which are globally controlled with a string select signal; and
a memory controller, coupled to the NAND memory array, the memory controller further determining a setup phase and a read phase, which does not overlap with the setup phase, wherein,
the memory controller provides a stream bias signal on a selected stream among the plurality of streams and provides a selected word line signal on a selected cell of the selected stream, in a setup phase;
the memory controller further provides a plurality of unselected word line signals on the rest of memory cells, to have the rest of memory cells turned on as pass transistors, in the setup phase;
the memory controller further provides a discharge path connected to the plurality of streams to accordingly eliminate coupling charge presented on at least an unselected stream among the plurality of streams, in the setup phase; and
the memory controller further enables the string select signal to have the selected stream connected to the sense unit via a metal bit line, so that the sense unit accordingly reads the selected cell in a voltage sensing scheme, in the read phase.

### Claim 6 (depends on 5)

The flash memory according to claim 5, wherein the memory controller enables the string select signal to have the plurality of streams globally connected to the metal bit line, and have the at least an unselected stream discharged via the metal bit line, to accordingly provide the discharge path.

### Claim 7 (depends on 5)

The flash memory according to claim 5, wherein the memory controller further determines a first sub-phase within the setup phase, and the memory controller provides the stream bias signal, the selected word line signal, and the plurality of unselected word line signals in the first sub-phase.

### Claim 8 (depends on 7)

The flash memory according to claim 7, wherein the memory controller further determines a second sub-phase within the setup phase, wherein the memory controller provides the discharge path in the second sub-phase.