# US 8,542,530 B2 · Apparatus for reducing the impact of program disturb > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,542,530 B2 - Document ID: US8542530B2 - Status: Granted - Kind: B2 - Application number: 13/588,202 - Filed: 2012-08-17 - Published: 2012-12-06 - Granted: 2013-09-24 - Earliest claimed: 2006-04-12 - Assignees: SanDisk Technologies LLC - Applicants: Gerrit Jan Hemink - Inventors: Gerrit Jan Hemink - Web page: https://patentgrep.com/patent/US8542530B2 ## CPC - G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different verify levels are used for a particular word line (or other grouping of storage elements) during a programming process. In another embodiment, different compare levels are used for a particular word (or other grouping of storage elements) during a read process. ## Claims ### Claim 1 A non-volatile storage system, comprising: non-volatile storage elements, said non-volatile storage elements include a first set of non-volatile storage elements connected to a particular word line, a second set of non-volatile storage elements connected to said particular word line, and a third set of non-volatile storage elements connected to a group of word lines different than said particular word line; and a managing circuit in communication with said non-volatile storage elements, said managing circuit programs said first set of non-volatile storage elements using a first set of target levels, said managing circuit programs said second set of non-volatile storage elements using a different set of target levels; said managing circuit programs said third set of non-volatile storage elements using a second set of target levels, at least one of said first set of target levels is different than a corresponding target level of said second set of target levels, at least one of said different set of target levels is different than a corresponding target level of said second set of target levels, said different set of target levels is different than said first set of target levels. ### Claim 2 (depends on 1) A non-volatile storage system according to claim 1, wherein: said particular word line is adjacent to a source control line. ### Claim 3 (depends on 1) A non-volatile storage system according to claim 1, wherein: said non-volatile storage elements are multi-state NAND flash memory devices. ### Claim 4 (depends on 1) A non-volatile storage system according to claim 1, wherein: said managing circuit reads said first set of non-volatile storage elements using a first read compare value, reads said second set of non-volatile storage elements using said first read compare value, and reads said third set of non-volatile storage elements using said first read compare value. ### Claim 5 A non-volatile storage system, comprising: non-volatile storage elements, said non-volatile storage elements include a first set of non-volatile storage elements connected to a particular word line, a second set of non-volatile storage elements connected to said particular word line, and a third set of non-volatile storage elements connected to a second set of word lines different from said particular word line; and one or more managing circuits in communication with said non-volatile storage elements, said one or more managing circuits cause sensing of said first set of non-volatile storage elements using a first target level, said one or more managing circuits cause sensing of said second set of non-volatile storage elements using a second target level, said one or more managing circuits cause sensing of said third set of non-volatile storage elements using a different target level, said first target level is different from said second target level, said different target level is different from said second target level, said different target level is different from said first target level. ### Claim 6 (depends on 5) The non-volatile storage system of claim 5, wherein: said sensing of said first set of non-volatile storage elements is performed during a verify step of a programming process. ### Claim 7 (depends on 6) The non-volatile storage system of claim 6, wherein: said first target level comprises a first verify voltage; and said second target level comprises a second verify voltage greater than said first verify voltage. ### Claim 8 (depends on 5) The non-volatile storage system of claim 5, wherein: said sensing of said first set of non-volatile storage elements is performed during a read operation. ### Claim 9 (depends on 8) The non-volatile storage system of claim 8, wherein: said first target level comprises a first read compare voltage; and said second target level comprises a second read compare voltage greater than said first read compare voltage. ### Claim 10 (depends on 5) The non-volatile storage system of claim 5, wherein: said first set of non-volatile storage elements is associated with a first set of odd bit lines connected to said particular word line; and said second set of non-volatile storage elements is associated with a first set of even bit lines connected to said particular word line. ### Claim 11 (depends on 5) The non-volatile storage system of claim 5, wherein: said second set of word lines includes a second word line adjacent to said particular word line. ### Claim 12 (depends on 5) The non-volatile storage system of claim 5, wherein: said particular word line is adjacent to a source control line. ### Claim 13 (depends on 5) The non-volatile storage system of claim 5, wherein: said particular word line is at an edge of a boosting region. ### Claim 14 A method for operating a non-volatile storage system, comprising: sensing a first set of non-volatile storage elements using a first set of compare voltages, said first set of non-volatile storage elements is connected to a particular word line; sensing a second set of non-volatile storage elements using a second set of compare voltages different from said first set of compare voltages, said second set of non-volatile storage elements is connected to said particular word line; and sensing a third set of non-volatile storage elements using a third set of compare voltages different from said first set of compare voltages and said second set of compare voltages, said third set of non-volatile storage elements is connected to a second set of word lines different from said particular word line. ### Claim 15 (depends on 14) The method of claim 14, wherein: said sensing a first set of non-volatile storage elements is performed during a verify step of a programming process. ### Claim 16 (depends on 15) The method of claim 15, wherein: said first set of compare voltages includes a first verify voltage; and said second set of compare voltages includes a second verify voltage greater than said first verify voltage. ### Claim 17 (depends on 14) The method of claim 14, wherein: said sensing a first set of non-volatile storage elements is performed during a read operation. ### Claim 18 (depends on 17) The method of claim 17, wherein: said first set of compare voltages includes a first read compare voltage; and said second set of compare voltages includes a second read compare voltage greater than said first read compare voltage. ### Claim 19 (depends on 14) The method of claim 14, wherein: said first set of non-volatile storage elements is associated with a first set of odd bit lines connected to said particular word line; and said second set of non-volatile storage elements is associated with a first set of even bit lines connected to said particular word line. ### Claim 20 (depends on 14) The method of claim 14, wherein: said first set of non-volatile storage elements is associated with a first page of data; and said second set of non-volatile storage elements is associated with a second page of data different from said first page of data. ### Claim 21 (depends on 14) The method of claim 14, wherein: said second set of word lines includes a second word line adjacent to said word line. ### Claim 22 (depends on 14) The method of claim 14, wherein: said first set of non-volatile storage elements and said second set of non-volatile storage elements are multi-state NAND flash memory devices. ### Claim 23 (depends on 14) The method of claim 14, wherein: said particular word line is adjacent to a source control line. ### Claim 24 (depends on 14) The method of claim 14, wherein: said particular word line is at an edge of a boosting region.