# US 8,542,528 B2 · Semiconductor device and method for driving semiconductor device

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- Number: US 8,542,528 B2
- Document ID: US8542528B2
- Status: Granted
- Kind: B2
- Application number: 13/197,438
- Filed: 2011-08-03
- Published: 2012-02-09
- Granted: 2013-09-24
- Earliest claimed: 2010-08-06
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Yusuke Sekine; Kiyoshi Kato
- Inventors: Yusuke Sekine; Kiyoshi Kato
- Web page: https://patentgrep.com/patent/US8542528B2

## CPC

- G11C 11/40: using transistors
- G11C 11/405: with three charge-transfer gates, e.g. MOS transistors, per cell
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 11/5685: {using storage elements comprising metal oxide memory material, e.g. perovskites}
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 13/003: {Cell access}
- G11C 13/0064: {Verifying circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)}
- G11C 7/00: Arrangements for writing information into, or reading information out from, a digital store (G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413)
- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C 13/0033: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 2211/4016: Memory devices with silicon-on-insulator cells
- G11C 2213/79: Array wherein the access device being a transistor
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A semiconductor device with a novel structure is provided, in which the operation voltage is reduced or the storage capacity is increased by reducing variation in the threshold voltages of memory cells after writing. The semiconductor device includes a plurality of memory cells each including a transistor including an oxide semiconductor and a transistor including a material other than an oxide semiconductor, a driver circuit that drives the plurality of memory cells, and a potential generating circuit that generates a plurality of potentials supplied to the driver circuit. The driver circuit includes a data buffer, a writing circuit that writes one potential of the plurality of potentials into each of the plurality of memory cells as data, a reading circuit that reads the data written into the memory cells, and a verifying circuit that verifies whether the read data agrees with data held in the data buffer or not.

## Claims

### Claim 1

A semiconductor device comprising:
a memory cell comprising a first transistor including an oxide semiconductor and a second transistor including a material other than the oxide semiconductor;
a driver circuit configured to drive the memory cell; and
a potential generating circuit configured to generate potentials supplied to the driver circuit,
wherein the driver circuit comprises:
a data buffer configured to hold a first data to be written into the memory cell;
a writing circuit configured to write a second data with one potential of the potentials into the memory cell in accordance with the first data;
a reading circuit configured to read the second data written into the memory cell; and
a verifying circuit configured to verify whether the second data agrees with the first data or not,
wherein the one potential is a write potential for the memory cell where the second data agrees with the first data, and
wherein the write potential is changed to another potential of the potentials, for the memory cell where the second data does not agree with the first data.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein levels of the potentials are different from each other.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1,
wherein the writing circuit is electrically connected to one of a source and a drain of the first transistor, and
wherein the reading circuit is electrically connected to one of a source and a drain of the second transistor.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the second transistor comprises a channel formation region provided in a substrate including a semiconductor material.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5, wherein the substrate is a single crystal semiconductor substrate or an SOI substrate.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein the oxide semiconductor comprises an oxide semiconductor material including In, Ga, and Zn.

### Claim 8

A semiconductor device comprising:
memory cells each comprising a first transistor including an oxide semiconductor and a second transistor including a material other than the oxide semiconductor;
a driver circuit configured to drive the memory cells; and
a potential generating circuit configured to generate potentials supplied to the driver circuit,
wherein the driver circuit comprises:
a data buffer configured to hold a first data to be written into the memory cells;
a writing circuit configured to write a second data with one potential of the potentials into the memory cells in accordance with the first data;
a reading circuit configured to read the second data written into the memory cells; and
a verifying circuit configured to verify whether the second data agrees with the first data or not,
wherein the one potential is a write potential for a part of the memory cells where the second data agree with the first data; and
wherein the write potential is changed to another potential of the potentials, for the others of the memory cells where the second data does not agree with the first data.

### Claim 9 (depends on 8)

The semiconductor device according to claim 8, wherein levels of the potentials are different from each other.

### Claim 10 (depends on 8)

The semiconductor device according to claim 8, wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor.

### Claim 11 (depends on 8)

The semiconductor device according to claim 8,
wherein the writing circuit is electrically connected to one of a source and a drain of the first transistor, and
wherein the reading circuit is electrically connected to one of a source and a drain of the second transistor.

### Claim 12 (depends on 8)

The semiconductor device according to claim 8, wherein the second transistor comprises a channel formation region provided in a substrate including a semiconductor material.

### Claim 13 (depends on 12)

The semiconductor device according to claim 12, wherein the substrate is a single crystal semiconductor substrate or an SOI substrate.

### Claim 14 (depends on 8)

The semiconductor device according to claim 8, wherein the oxide semiconductor comprises an oxide semiconductor material including In, Ga, and Zn.

### Claim 15

A method for driving a semiconductor device comprising a memory cell comprising a first transistor including an oxide semiconductor and a second transistor including a material other than the oxide semiconductor, the method comprising the steps of:
holding a first data to be written into the memory cell in a data buffer;
writing a second data with one potential of potentials into the memory cell in accordance with the first data;
reading the second data written into the memory cell;
verifying whether the second data agrees with the first data or not; and
determining the one potential as a first write potential for the memory cell where the second data agrees with the first data, or changing the first write potential to another potential of the potentials, for the memory cell where the second data does not agree with the first data.

### Claim 16 (depends on 15)

The method for driving the semiconductor device according to claim 15, further comprising the steps of:
writing the second data with the another potential into the memory cell after changing the first write potential to the another potential;
reading the second data written into the memory cell;
verifying whether the second data agrees with the first data or not; and
determining the another potential as a second write potential for the memory cell where the second data agrees with the first data, or changing the second write potential to still another potential of the potentials, for the memory cell where the second data does not agree with the first data.

### Claim 17 (depends on 15)

The method for driving the semiconductor device according to claim 15, wherein levels of the potential are different from each other.

### Claim 18 (depends on 15)

The method for driving the semiconductor device according to claim 15, wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor.

### Claim 19 (depends on 15)

The method for driving the semiconductor device according to claim 15, wherein the second transistor comprises a channel formation region provided in a substrate including a semiconductor material.

### Claim 20 (depends on 19)

The method for driving the semiconductor device according to claim 19, wherein the substrate is a single crystal semiconductor substrate or an SOI substrate.

### Claim 21 (depends on 15)

The method for driving the semiconductor device according to claim 15, wherein the oxide semiconductor comprises an oxide semiconductor material including In, Ga, and Zn.

### Claim 22

A method for driving a semiconductor device comprising memory cells each comprising a first transistor including an oxide semiconductor and a second transistor including a material other than the oxide semiconductor, the method comprising the steps of:
holding a first data to be written into the memory cells in a data buffer;
writing a second data with one potential of potentials into the memory cells in accordance with the first data;
reading the second data written into the memory cells;
verifying whether the second data agrees with the first data or not;
determining the one potential as a first write potential for a first part of the memory cells where the second data agrees with the first data; and
changing the first write potential to another potential of the potentials, for a second part of the memory cells where the second data does not agree with the first data.

### Claim 23 (depends on 22)

The method for driving the semiconductor device according to claim 22, further comprising the steps of:
writing the second data with the another potential into the second part of the memory cells after changing the first write potential to the another potential;
reading the second data written into the second part of the memory cells,
verifying whether the second data agrees with the first data or not;
determining the another potential as a second write potential for the second part of the memory cells where the second data agree with the first data after verifying; and
changing the second write potential to still another potential of the potentials, for a third part of the memory cells where the second data does not agree with the first data.

### Claim 24 (depends on 22)

The method for driving the semiconductor device according to claim 22, wherein levels of the potentials are different from each other.

### Claim 25 (depends on 22)

The method for driving the semiconductor device according to claim 22, wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor.

### Claim 26 (depends on 22)

The method for driving the semiconductor device according to claim 22, wherein the second transistor comprises a channel formation region provided in a substrate including a semiconductor material.

### Claim 27 (depends on 26)

The method for driving the semiconductor device according to claim 26, wherein the substrate is a single crystal semiconductor substrate or an SOI substrate.

### Claim 28 (depends on 22)

The method for driving the semiconductor device according to claim 22, wherein the oxide semiconductor comprises an oxide semiconductor material including In, Ga, and Zn.