# US 8,542,524 B2 · Magnetic random access memory (MRAM) manufacturing process for a small magnetic tunnel junction (MTJ) design with a low programming current requirement

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,542,524 B2
- Document ID: US8542524B2
- Status: Granted
- Kind: B2
- Application number: 12/975,304
- Filed: 2010-12-21
- Published: 2011-04-21
- Granted: 2013-09-24
- Earliest claimed: 2007-02-12
- Assignees: Avalanche Technology, Inc.
- Applicants: Parviz Keshtbod; Roger Klas Malmhall; Rajiv Yadav Ranjan
- Inventors: Parviz Keshtbod; Roger Klas Malmhall; Rajiv Yadav Ranjan
- Web page: https://patentgrep.com/patent/US8542524B2

## CPC

- H10N 50/01: Manufacture or treatment
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell}
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10N 50/10: Magnetoresistive devices
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method of making a magnetic random access memory cell includes forming a magnetic tunnel junction (MTJ) on top of a wafer, depositing oxide on top of the MTJ, depositing a photo-resist layer on top of the oxide layer, forming a trench in the photo-resist layer and oxide layer where the trench has a width that is substantially the same as that of the MTJ. Then, the photo-resist layer is removed and a hard mask layer is deposited on top of the oxide layer in the trench and the wafer is planarized to remove the portion of the hard mask layer that is not in the trench to substantially level the top of oxide layer and the hard layer on the wafer. The remaining oxide layer is etched and the MTJ is etched to remove the portion of the MTJ which is not covered by the hard mask layer.

## Claims

### Claim 1

A magnetic random access memory cell, comprising:
a complimentary metal-oxide-semiconductor (CMOS) wafer;
a conductive layer formed on top of the CMOS wafer;
a magnetic tunnel junction (MTJ) centered on top of the conductive layer;
a hard mask layer, formed on top of the MTJ; and
a shielding layer, wherein the shielding layer covers the hard mask layer, the sides of the MTJ, and the exposed portion of the conductive layer.

### Claim 2 (depends on 1)

A magnetic random access memory cell, as recited in claim 1, further comprising:
a oxide layer, formed on top of the shielding layer;
a second shielding layer, formed on top of the oxide layer;
a second oxide layer, formed on top of the second shielding layer;
a second conductive layer; and
a MTJ trench, wherein the trench is filled with the second conductive layer, and the trench spans from the top of the second oxide layer down through the second oxide layer, second shielding layer, oxide layer, and first shielding layer such that the top of the hard mask layer forms the bottom of MTJ trench.

### Claim 3 (depends on 1)

A magnetic random access memory cell, as recited in claim 1, further comprising:
a via trench, wherein the trench is filled with the second conductive layer, and the trench spans from the top of the second oxide layer down through the second oxide layer, second shielding layer, oxide layer, and first shielding layer such that the conductive layer forms the bottom of the via trench.