# US 8,542,522 B2 · Non-volatile data-storage latch

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,542,522 B2
- Document ID: US8542522B2
- Status: Granted
- Kind: B2
- Application number: 13/259,164
- Filed: 2009-07-23
- Published: 2012-01-19
- Granted: 2013-09-24
- Earliest claimed: 2009-07-23
- Assignees: Hewlett-Packard Development Company, L.P.
- Applicants: Gregory Stuart Snider
- Inventors: Gregory Stuart Snider
- Web page: https://patentgrep.com/patent/US8542522B2

## CPC

- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 5/141: {Battery and back-up supplies}
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 14/00: Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C 19/00: Digital stores in which the information is moved stepwise, e.g. shift registers
- H03K 3/45: by the use, as active elements, of non-linear magnetic or dielectric devices
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

One embodiments of the present invention is directed to a single-bit memory cell comprising transistor-based bit latch having a data state and a memristor, coupled to the transistor-based bit latch, in which the data state of the transistor-based bit latch is stored by a store operation and from which a previously-stored data state is retrieved and restored into the transistor-based bit latch by a restore operation. Another embodiment of the present invention is directed to a single-bit memory cell comprising a master-slave flip flop and a slave flip flop, and a power input, a memristor, a memory-cell power input, a first memory-cell clock input, a second memory-cell clock input, a memory-cell data input, a memory-cell data output, and two or more memory-cell control inputs.

## Claims

### Claim 1

A single-bit memory cell comprising:
a transistor-based bit latch having a data state; and
a memristor, coupled to the transistor-based bit latch, in which the data state of the transistor-based bit latch is stored by a store operation and from which a previously-stored data state is retrieved and restored into the transistor-based bit latch by a restore operation.

### Claim 2 (depends on 1)

The single-bit memory cell of claim 1 wherein the data state of the transistor-based bit latch is stored as an impedance state in the memristor.

### Claim 3 (depends on 1)

The single-bit memory cell of claim 1 further including at least two input signals to which control signals are input in order to store the current data state of the transistor-based bit latch in the memristor.

### Claim 4 (depends on 1)

The single-bit memory cell of claim 1 further including at least two input signals to which control signals are input in order to restore the data state of the transistor-based bit latch from a data state stored in the memristor.

### Claim 5 (depends on 1)

A memory element comprising two or more single-bit memory cells of claim 1.

### Claim 6 (depends on 1)

The single-bit memory cell of claim 1, further comprising a power-down state machine that is activated by detecting a power-failure event, said power-down state machine, when activated by detecting a power-failure event, capturing a current data state of said transistor-based bit latch as a corresponding resistance level in said memristor.

### Claim 7

A single-bit memory cell comprising:
a master-slave flip flop comprising a master flip flop and a slave flip flop, each of the master flip flop and slave flip flop having a data input, a data output, a clock input, and a power input;
a memristor;
a memory-cell power input;
a first memory-cell clock input;
a second memory-cell clock input;
a memory-cell data input;
a memory-cell data output; and
two or more memory-cell control inputs.

### Claim 8 (depends on 7)

The single-bit memory cell of claim 7 wherein the two or more memory-cell control inputs include:
a power-up input;
a power-down input;
a P1 input; and
a P2 input.

### Claim 9 (depends on 8)

The single-bit memory cell of claim 8 wherein:
the memory-cell data input is coupled to the data input of the master flip flop;
the memory-cell data output is coupled to the data output of the slave flip flop;
the memory-cell power input is coupled to the power input of the master flip flop and to the power input of the slave flip flop
the first memory-cell clock input is coupled to the clock input of the master flip flop;
the second memory-cell clock input is coupled to the clock input of the slave flip flop;
the data input of the slave flip flop is connected to the output of a multiplexer, a first input of which is connected to the data output of the master D flip flop, the multiplexer controlled by the power-up input;
the memristor is connected, on a first side, to the P1 input and is connected, on a second side, through a circuit point and resistor to the P2 input; and
a switch, controlled by the power-down input, is connected to the data output of the master D flip flop, on a first side, and connected, on a second side, through the circuit point to a second input of the multiplexer.

### Claim 10 (depends on 8)

The single-bit memory cell of claim 8 wherein a current data state of the master flip flop is saved in the memristor by:
applying system voltage V to the P2 input and connecting the P1 input to ground; and
while applying system voltage V to the P1 input and connecting the P2 input to ground, asserting power-down.

### Claim 11 (depends on 8)

The single-bit memory cell of claim 8 wherein a data state stored in the memristor is restored to the of the slave flip flop by:
while applying system voltage V to the P1 input and connecting the P2 input to ground, asserting the power-up input and asserting the clock input to the slave flip flop.

### Claim 12 (depends on 8)

The single-bit memory cell of claim 8 that operates normally when:
the P2 and the P1 are both in high-impedance states; and
the power-down and power-up inputs are not asserted.

### Claim 13 (depends on 12)

The single-bit memory cell of claim 12 that, during normal operation:
latches a data value input to the memory-cell data input when the second memory-cell clock is asserted following assertion of the first memory-cell clock and outputs the latched data value to the memory-cell data output.

### Claim 14 (depends on 8)

A memory element comprising two or more memory cells of claim 8 that share a common first memory-cell clock input; second memory-cell clock input; power-up input; power-down input; P1 input; and P2 input.

### Claim 15 (depends on 14)

A system that includes memory elements of claim 14.

### Claim 16 (depends on 15)

The system of claim 15 further including a capacitor or battery charged by a power input that, when the system power input falls below a threshold voltage, discharges into a power-down state machine that stores the data states of the memory cells of the memory elements into memristors incorporated into the memory cells.

### Claim 17 (depends on 15)

The system of claim 15 further including power-up logic that:
determines whether or not, on a previous power down, the data states of the memory cells of the memory elements were stored into memristors incorporated into the memory cells; and
when, on a previous power down, the data states of the memory cells of the memory elements were stored into memristors incorporated into the memory cells, restores the data states stored in the memristors of the memory cells into the memory cells.

### Claim 18 (depends on 6)

The single-bit memory cell of claim 6, wherein, when activated by detecting a power-failure event, said power-down state machine sets a resistance level of said memristor to a low state and then maintains or changes that resistance level of said memristor based on said current data state of said transistor-based bit latch.

### Claim 19 (depends on 6)

The single-bit memory cell of claim 6, further comprising a capacitor for storing charge with which said power-down state machine powers capture of said current data state of said transistor-based bit latch as a corresponding resistance level in said memristor in response to detection of a power-failure event.

### Claim 20

A method of storing data in a single-bit memory cell comprising:
selectively storing either of two data states with a transistor-based bit latch; and
storing a current data state of said transistor-basted bit latch with a memristor coupled to the transistor-based bit latch,
such that a previously-stored data state is selectively retrieved and restored into the transistor-based bit latch from the memristor.