# US 8,542,514 B1 · Memory structure having SRAM cells and SONOS devices

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- Number: US 8,542,514 B1
- Document ID: US8542514B1
- Status: Granted
- Kind: B1
- Application number: 12/242,285
- Filed: 2008-09-30
- Granted: 2013-09-24
- Earliest claimed: 2008-09-30
- Assignees: Cypress Semiconductor Corporation
- Applicants: Sethuraman Lakshminarayanan; Myongseob Kim
- Inventors: Sethuraman Lakshminarayanan; Myongseob Kim
- Web page: https://patentgrep.com/patent/US8542514B1

## CPC

- G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C 14/0054: {in which the volatile element is a SRAM cell}
- G11C 14/0063: {and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory structure and method to fabricate the same is described. The memory structure includes a first memory cell having a first pair of non-volatile portions. The memory structure also includes a second memory cell having a second pair of non-volatile portions. The first and second pairs of non-volatile portions are disposed in an inter-locking arrangement.

## Claims

### Claim 1

A memory structure, comprising:
a first memory cell having a first plurality of non-volatile Semiconductor-Oxide-Nitride-Oxide-Semiconductor type (SONOS-type) devices coupled with a first Six Transistor (6-T) Static Random Access Memory (SRAM) cell;
a second memory cell having a second plurality of non-volatile SONOS-type devices coupled with a second 6-T SRAM cell, wherein the first plurality of non-volatile SONOS-type devices are interdigitated with the second plurality of non-volatile SONOS-type devices;
a store gate line, a non-volatile gate line, and a recall gate line, wherein the store gate line, the non-volatile gate line, and the recall gate line overlap diffusion areas of both the first and second pluralities of non-volatile SONOS-type devices; and
wherein each of the first and the second pluralities of non-volatile SONOS-type devices comprises an interconnect and a set of dummy interconnects.

### Claim 2 (depends on 1)

The memory structure of claim 1, wherein the set of dummy interconnects is provided for increasing an electrical symmetry of the first and second memory cells by reducing a capacitance difference between the first and second memory cells.

### Claim 3 (depends on 1)

The memory structure of claim 1, wherein the SONOS-type devices are 65 nanometer node devices.

### Claim 4 (depends on 1)

The memory structure of claim 1, wherein the combination of the first and second memory cells has a total area, and wherein the total area of the first and second memory cells combined is approximately 2.5 by approximately 1.4 square microns.

### Claim 5 (depends on 1)

The memory structure of claim 1, wherein alternating ones of the first plurality of non-volatile SONOS-type devices are interdigitated with corresponding alternating ones of the second plurality of non-volatile SONOS-type devices.

### Claim 6

A method for fabricating a memory structure, comprising:
forming a first memory cell having a first plurality of non-volatile Semiconductor-Oxide-Nitride-Oxide-Semiconductor type (SONOS-type) devices coupled with a first Six Transistor (6-T) Static Random Access Memory (SRAM) cell;
forming a second memory cell having a second plurality of non-volatile SONOS-type devices coupled with a second 6-T SRAM cell, wherein the first plurality of non-volatile SONOS-type devices are interdigitated with the second plurality of non-volatile SONOS-type devices;
forming a store gate line, a non-volatile gate line, and a recall gate line, wherein each of the store gate line, the non-volatile gate line, and the recall gate line overlaps diffusion areas of both the first and second pluralities of non-volatile SONOS-type devices; and
forming a plurality of interconnects and a plurality of dummy interconnects, wherein each of the first and second pluralities of non-volatile SONOS-type devices is coupled with one of the plurality of interconnects and one of the plurality of dummy interconnects.

### Claim 7 (depends on 6)

The method of claim 6, wherein forming the plurality of dummy interconnects comprises increasing an electrical symmetry of the first and second memory cells by reducing a capacitance difference between the first and second memory cells.

### Claim 8 (depends on 6)

The method of claim 6, wherein forming the SONOS-type devices comprises forming 65 nanometer node devices.

### Claim 9 (depends on 6)

The method of claim 6, wherein forming the first and second memory cells comprises forming the first and second memory cells to have a combined total area of approximately 2.5 by approximately 1.4 square microns.

### Claim 10 (depends on 6)

The method of claim 6, wherein alternating ones of the first plurality of non-volatile SONOS-type devices are interdigitated with corresponding alternating ones of the second plurality of non-volatile SONOS-type devices.