# US 8,542,222 B2 · Differential amplifier circuit, data line driver using the same, and liquid crystal display apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,542,222 B2 - Document ID: US8542222B2 - Status: Granted - Kind: B2 - Application number: 12/822,832 - Filed: 2010-06-24 - Published: 2011-02-03 - Granted: 2013-09-24 - Earliest claimed: 2009-07-30 - Assignees: Renesas Electronics Corporation - Applicants: Kouichi Nishimura; Toshikazu Murata - Inventors: Kouichi Nishimura; Toshikazu Murata - Web page: https://patentgrep.com/patent/US8542222B2 ## CPC - H03F 3/45219: {Folded cascode stages} - H03F 3/3022: {CMOS common source output SEPP amplifiers (H03F3/3008 takes precedence)} - H03F 3/45192: {Folded cascode stages} - G09G 3/3688: {suitable for active matrices only} - G09G 2310/027: Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters - H03F 2203/45631: the LC comprising one or more capacitors, e.g. coupling capacitors - H03F: AMPLIFIERS - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A differential amplifier circuit includes: an NMOS transistor pair connected with a non-inversion input terminal and an inversion input terminal; a PMOS transistor pair connected with the non-inversion input terminal and the inversion input terminal; and an output circuit section. The PMOS transistor pair includes first and second PMOS transistors, and the NMOS transistor pair includes first and second non-doped type NMOS transistors as a depletion type of NMOS transistors in which a channel region is formed in a P-type substrate without a P well. The output circuit section includes a first current mirror of a folded cascode type connected with the first and second non-doped type NMOS transistors, and outputs an output voltage in response to a current from the first current mirror. ## Claims ### Claim 1 A differential amplifier circuit comprising: an NMOS transistor pair connected with a non-inversion input terminal and an inversion input terminal; a PMOS transistor pair connected with said non-inversion input terminal and said inversion input terminal; and an output circuit section, wherein said PMOS transistor pair comprises first and second PMOS transistors, wherein said NMOS transistor pair comprises first and second non-doped type NMOS transistors as a depletion type of NMOS transistors in which a channel region is formed in a P-type substrate without a P well, and wherein said output circuit section comprises a first current mirror of a folded cascode type connected with said first and second non-doped type NMOS transistors, and outputs an output voltage in response to a current from said first current mirror. ### Claim 2 (depends on 1) The differential amplifier circuit according to claim 1, wherein a threshold voltage of said non-doped type NMOS transistor is in a range of −0.2 to 0 V. ### Claim 3 (depends on 1) The differential amplifier circuit according to claim 1, wherein said first current mirror comprises third to sixth PMOS transistors, wherein said third and fourth PMOS transistors have source connected in common to a power supply line, gates connected in common, and drains respectively connected with sources of said fifth and sixth PMOS transistors, wherein first bias voltage is applied to gates of said fifth and sixth PMOS transistors in common, wherein a drain of said fifth PMOS transistor is connected in common to the gates of said third and fourth PMOS transistors, wherein said first and second non-doped type NMOS transistors have sources connected in common to a first current source, drains respectively connected with the drains of said fourth and third PMOS transistors, and gates respectively connected with said non-inversion input terminal and said inversion input terminal, and wherein said output circuit section generates said output voltage in response to the current flowing from sixth PMOS transistor. ### Claim 4 (depends on 3) The differential amplifier circuit according to claim 3, wherein said output circuit section further comprises: a second current mirror connected with said first and second PMOS transistors; a floating current source connected between said first current mirror and said second current mirror; a first output transistor as a PMOS transistor having a drain connected with an output terminal from which said output voltage is outputted, a gate connected with one end of said floating current source, and a second output transistor as an NMOS transistor having a drain connected with said output terminal and a gate connected with the other end of said floating current source. ### Claim 5 (depends on 4) The differential amplifier circuit according to claim 4, wherein said second current mirror comprises third to sixth NMOS transistors, wherein said third and fourth NMOS transistors have sources connected in common to a ground line, gates connected in common, and drains connected with sources of said fifth and sixth NMOS transistors, respectively, wherein a second bias voltage is supplied to gates of said fifth and sixth NMOS transistors, wherein a drain of said fifth PMOS transistor is connected in common to the gates of said third and fourth PMOS transistors, wherein said first and second PMOS transistors have sources connected in common to a second current source, drains connected with drains of said fourth and third NMOS transistors, and gates connected with said non-inversion input terminal and said inversion input terminal, respectively, wherein a third current source is connected between the drain of said fifth NMOS transistor and the drain of said fifth PMOS transistor, wherein said floating current source comprises a seventh PMOS transistor having a gate to which a third bias voltage is supplied and a seventh NMOS transistor having a gate to which a fourth bias voltage is supplied, wherein said seventh PMOS transistor has a source connected with the drain of said sixth PMOS transistor with a drain connected with said seventh NMOS transistor, and wherein said seventh NMOS transistor has a drain connected with the drain of said sixth PMOS transistor and a source connected with the drain of said sixth NMOS transistor. ### Claim 6 A data line driver comprising: a D/A (digital-to-analog) converter configured to output a gray scale voltage corresponding to a display data; and a differential amplifier circuit comprising an output terminal connected with a data line of a liquid crystal display panel, and having a non-inversion input terminal connected with said gray scale voltage and an inversion input terminal connected with said output terminal, wherein said differential amplifier circuit comprises: an NMOS transistor pair connected with said non-inversion input terminal and said inversion input terminal; a PMOS transistor pair connected with said non-inversion input terminal and said inversion input terminal; and an output circuit section, wherein said PMOS transistor pair comprises first and second PMOS transistors, wherein said NMOS transistor pair comprises first and second non-doped type NMOS transistors as a depletion type of NMOS transistors in which a channel region is formed in a P-type substrate without a P well, and wherein said output circuit section comprises a first current mirror of a folded cascode type connected with said first and second non-doped type NMOS transistors, and output an output voltage to said output terminal in response to a current from said first current mirror. ### Claim 7 (depends on 6) The data line driver according to claim 6, wherein a threshold voltage of said non-doped type NMOS transistor is in a range of −0.2 to 0 V. ### Claim 8 (depends on 6) The data line driver according to claim 6, wherein said first current mirror comprises a third to sixth PMOS transistors, wherein said third and fourth PMOS transistors have source connected in common to a power supply line, gates connected in common, and drains respectively connected with sources of said fifth and sixth PMOS transistors, wherein first bias voltage is applied to gates of said fifth and sixth PMOS transistors in common, wherein a drain of said fifth PMOS transistor is connected in common to the gates of said third and fourth PMOS transistors, wherein said first and second non-doped type NMOS transistors have sources connected in common to a first current source, drain respectively connected with the drains of said fourth and third PMOS transistors, and gates respectively connected with said non-inversion input terminal and said inversion input terminal, and wherein said output circuit section generates said output voltage in response to the current flowing from sixth PMOS transistor. ### Claim 9 (depends on 8) The data line driver according to claim 8, wherein said output circuit section further comprises: a second current mirror connected with said first and second PMOS transistors; a floating current source connected between said first current mirror and said second current mirror; a first output transistor as a PMOS transistor having a drain connected with said output terminal from which said output voltage is outputted, a gate connected with one end of said floating current source, and a second output transistor as an NMOS transistor having a drain connected with said output terminal and a gate connected with the other end of said floating current source. ### Claim 10 (depends on 9) The data line driver according to claim 9, wherein said second current mirror comprises third to sixth NMOS transistors, wherein said third and fourth NMOS transistors have sources connected in common to a ground line, gates connected in common, and drains connected with sources of said fifth and sixth NMOS transistors, respectively, wherein a second bias voltage is supplied to gates of said fifth and sixth NMOS transistors, wherein a drain of said fifth PMOS transistor is connected in common to the gates of said third and fourth PMOS transistors, wherein said first and second PMOS transistors have sources connected in common to a second current source, drains connected with drains of said fourth and third NMOS transistors, and gates connected with said non-inversion input terminal and said inversion input terminal, respectively, wherein a third current source is connected between the drain of said fifth NMOS transistor and the drain of said fifth PMOS transistor, wherein said floating current source comprises a seventh PMOS transistor having a gate to which a third bias voltage is supplied and a seventh NMOS transistor having a gate to which a fourth bias voltage is supplied, wherein said seventh PMOS transistor has a source connected with the drain of said sixth PMOS transistor with a drain connected with said seventh NMOS transistor, and wherein said seventh NMOS transistor has a drain connected with the drain of said sixth PMOS transistor and a source connected with the drain of said sixth NMOS transistor. ### Claim 11 A liquid crystal display apparatus comprising: a liquid crystal display panel; and a data line driver configured to drive a data line of said liquid crystal display panel, wherein said data line driver comprises: a D/A (digital-to-analog) converter configured to output a gray scale voltage corresponding to a display data; and a differential amplifier circuit comprising an output terminal connected with said data line of a liquid crystal display panel, and having a non-inversion input terminal connected with said gray scale voltage and an inversion input terminal connected with said output terminal, wherein said differential amplifier circuit comprises: an NMOS transistor pair connected with said non-inversion input terminal and said inversion input terminal; a PMOS transistor pair connected with said non-inversion input terminal and said inversion input terminal; and an output circuit section, wherein said PMOS transistor pair comprises first and second PMOS transistors, wherein said NMOS transistor pair comprises first and second non-doped type NMOS transistors as a depletion type of NMOS transistors in which a channel region is formed in a P-type substrate without a P well, and wherein said output circuit section comprises a first current mirror of a folded cascode type connected with said first and second non-doped type NMOS transistors, and outputs an output voltage to said output terminal in response to a current from said first current mirror. ### Claim 12 (depends on 11) The liquid crystal display apparatus according to claim 11, wherein a threshold voltage of said non-doped type NMOS transistor is in a range of −0.2 to 0 V. ### Claim 13 (depends on 11) The liquid crystal display apparatus according to claim 11, wherein said first current mirror comprises third to sixth PMOS transistors, wherein said third and fourth PMOS transistors have source connected in common to a power supply line, gates connected in common, and drains respectively connected with sources of said fifth and sixth PMOS transistors, wherein first bias voltage is applied to gates of said fifth and sixth PMOS transistors in common, wherein a drain of said fifth PMOS transistor is connected in common to the gates of said third and fourth PMOS transistors, wherein said first and second non-doped type NMOS transistors have sources connected in common to a first current source, drains respectively connected with the drains of said fourth and third PMOS transistors, and gates respectively connected with said non-inversion input terminal and said inversion input terminal, and wherein said output circuit section generates said output voltage in response to the current flowing from sixth PMOS transistor. ### Claim 14 (depends on 13) The liquid crystal display apparatus according to claim 13, wherein said output circuit section further comprises: a second current mirror connected with said first and second PMOS transistors; a floating current source connected between said first current mirror and said second current mirror; a first output transistor as a PMOS transistor having a drain connected with said output terminal from which said output voltage is outputted, a gate connected with one end of said floating current source, and a second output transistor as an NMOS transistor having a drain connected with said output terminal and a gate connected with the other end of said floating current source. ### Claim 15 (depends on 14) The liquid crystal display apparatus according to claim 14, wherein said second current mirror comprises third to sixth NMOS transistors, wherein said third and fourth NMOS transistors have sources connected in common to a ground line, gates connected in common, and drains connected with sources of said fifth and sixth NMOS transistors, respectively, wherein a second bias voltage is supplied to gates of said fifth and sixth NMOS transistors, wherein a drain of said fifth PMOS transistor is connected in common to the gates of said third and fourth PMOS transistors, wherein said first and second PMOS transistors have sources connected in common to a second current source, drains connected with drains of said fourth and third NMOS transistors, and gates connected with said non-inversion input terminal and said inversion input terminal, respectively, wherein a third current source is connected between the drain of said fifth NMOS transistor and the drain of said fifth PMOS transistor, wherein said floating current source comprises a seventh PMOS transistor having a gate to which a third bias voltage is supplied and a seventh NMOS transistor having a gate to which a fourth bias voltage is supplied, wherein said seventh PMOS transistor has a source connected with the drain of said sixth PMOS transistor with a drain connected with said seventh NMOS transistor, and wherein said seventh NMOS transistor has a drain connected with the drain of said sixth PMOS transistor and a source connected with the drain of said sixth NMOS transistor.