# US 8,542,177 B2 · Data driving apparatus and display device comprising the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,542,177 B2 - Document ID: US8542177B2 - Status: Granted - Kind: B2 - Application number: 12/472,902 - Filed: 2009-05-27 - Published: 2010-04-15 - Granted: 2013-09-24 - Earliest claimed: 2008-10-14 - Assignees: Samsung Display Co., Ltd. - Applicants: Whee-won Lee - Inventors: Whee-won Lee - Web page: https://patentgrep.com/patent/US8542177B2 ## CPC - G09G 3/3688: {suitable for active matrices only} - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A data driving apparatus includes a horizontal synchronization start signal generation circuit and data driving circuit. The horizontal synchronization start signal generation circuit generates a horizontal synchronization start signal using image data signals. The data driving circuit samples the image data signals in response to the horizontal synchronization start signal and supplies a plurality of data signals using the sampled image data signals in response to a load signal. The horizontal synchronization start signal generation circuit is disabled in response to the load signal. ## Claims ### Claim 1 A data driving apparatus comprising: a horizontal synchronization start signal generation circuit that generates a horizontal synchronization start signal using image data signals; and a data driving circuit that samples the image data signals in response to the horizontal synchronization start signal and supplies a plurality of data signals using the sampled image data signals in response to a load signal, wherein the horizontal synchronization start signal generation circuit is disabled in response to the load signal, wherein the horizontal synchronization start signal generation circuit generates the horizontal synchronization start signal when at least two last bits of the image data signals are a same logic level, and wherein the horizontal synchronization start signal is derived from the at least two last bits. ### Claim 2 (depends on 1) The data driving apparatus of claim 1, wherein the image data signals have a horizontal synchronization start signal generation period and an effective image data period, the data driving circuit provides the respective data signals in the effective image data period using j bits of the image data signals, and the horizontal synchronization start signal generation circuit provides the horizontal synchronization start signal using k bits of the image data signals included in the horizontal synchronization start signal generation period, wherein j and k are natural numbers. ### Claim 3 (depends on 2) The data driving apparatus of claim 2, wherein the horizontal synchronization start signal generation circuit generates the horizontal synchronization start signal when the k bits of the image data signals included in the horizontal synchronization start signal generation period are all at high levels. ### Claim 4 (depends on 2) The data driving apparatus of claim 2, wherein k is less than j. ### Claim 5 (depends on 1) The data driving apparatus of claim 1, wherein the horizontal synchronization start signal generation circuit comprises: a plurality of flip-flops that are connected to one another in a cascade manner, supplied with and sequentially outputting the image data signals; and an operation unit that performs an operation on output signals supplied from at least two flip-flops among the plurality of flip-flops. ### Claim 6 (depends on 5) The data driving apparatus of claim 5, wherein the load signal is input to a reset terminal of each of the plurality of flip-flops. ### Claim 7 (depends on 6) The data driving apparatus of claim 6, wherein the load signal or a delayed signal of the load signal is input to a reset terminal of each of the plurality of flip-flops. ### Claim 8 (depends on 5) The data driving apparatus of claim 5, wherein the operation unit performs AND operations on output signals supplied from at least two flip-flops among the plurality of flip-flops. ### Claim 9 (depends on 1) The data driving apparatus of claim 1, wherein the data driving circuit comprises: a shift register that samples the image data signals in response to the horizontal synchronization start signal and a data sampling clock signal, and outputs the sampled image data signals in response to the load signal; a digital-to-analog converter that receives the sampled image data signals from the shift register and outputs a plurality of analog data signals corresponding to the sampled data signals; and a buffer that is supplied with the plurality of analog data signals, selects polarities of the analog data signals and provides the selected polarities to the data signals. ### Claim 10 A data driving apparatus comprising: a horizontal synchronization start signal generation circuit that generates a horizontal synchronization start signal when at least two last bits of image data signals are a same logic level, the horizontal synchronization start signal being derived from the at least two last bits, the horizontal synchronization start signal generation circuit including a plurality of flip-flops that are connected to one another in a cascade manner, supplied with and sequentially outputting the image data signals, and an operation unit that performs a logical operation on output signals supplied from at least two flip-flops among the plurality of flip-flops to generate the horizontal synchronization start signal, wherein the logical operation indicates whether all of the output signals supplied from the at least two flip-flops to the operation unit have a same logic level; a shift register that samples the image data signals in response to the horizontal synchronization start signal and a data sampling clock signal, and outputs the sampled image data signals in response to a load signal; a digital-to-analog converter that receives the sampled image data signals from the shift register and outputs a plurality of analog data signals corresponding to the sampled data signals; and a buffer that is supplied with the plurality of analog data signals, selects polarities of the analog data signals and provides the selected polarities to the data signals, wherein the horizontal synchronization start signal generation circuit is disabled in response to the load signal. ### Claim 11 (depends on 10) The data driving apparatus of claim 10, wherein the load signal is input to a reset terminal of each of the plurality of flip-flops of the horizontal synchronization start signal generation circuit. ### Claim 12 (depends on 11) The data driving apparatus of claim 11, wherein the load signal or a delayed signal of the load signal is input to a reset terminal of each of the plurality of flip-flops of the horizontal synchronization start signal generation circuit. ### Claim 13 (depends on 10) The data driving apparatus of claim 10, wherein the image data signals have a horizontal synchronization start signal generation period and an effective image data period, the respective data signals are provided in the effective image data period using j bits of the image data signals, and the horizontal synchronization start signal generation circuit provides the horizontal synchronization start signal using k bits of the image data signals included in the horizontal synchronization start signal generation period, wherein j and k are natural numbers. ### Claim 14 A display device comprising: a display panel that includes a plurality of unit pixels at intersections of a plurality of gate lines and a plurality of data lines; a timing controller that provides data control signals and image data signals; and a data driver that applies data signals to the plurality of data lines in response to the data control signals and the image data signal, the data driver comprising: a horizontal synchronization start signal generation circuit that generates a horizontal synchronization start signal from an output of a logical operation performed on image data signals, wherein the horizontal synchronization start signal is generated when the logical operation indicates that at least two last bits of the image data signals are a same logic level, the horizontal synchronization start signal being an output of the logical operation; and a data driving circuit that samples the image data signals in response to the horizontal synchronization start signal and supplies a plurality of data signals using the sampled image data signals in response to a load signal, wherein the horizontal synchronization start signal generation circuit is disabled in response to the load signal. ### Claim 15 (depends on 14) The display device of claim 14, wherein the horizontal synchronization start signal generation circuit comprises: a plurality of flip-flops that are connected to one another in a cascade manner, supplied with and sequentially outputting the image data signals; and an operation unit that performs the logical operation on output signals supplied from at least two flip-flops among the plurality of flip-flops, wherein the logical operation indicates whether all of the output signals supplied from the least two flip-flops to the operation unit are a same logic level; wherein the data driving circuit comprises: a shift register that samples the image data signals in response to the horizontal synchronization start signal and a data sampling clock signal, and outputs the sampled image data signals in response to a load signal; a digital-to-analog converter that receives the sampled image data signals from the shift register and outputs a plurality of analog data signals corresponding to the sampled data signals; and a buffer that is supplied with the plurality of analog data signals, selects polarities of the analog data signals and provides the selected polarities to the data signals. ### Claim 16 (depends on 15) The display device of claim 15, wherein the load signal is input to a reset terminal of each of the plurality of flip-flops. ### Claim 17 (depends on 16) The display device of claim 16, wherein the load signal or a delayed signal of the load signal is input to a reset terminal of each of the plurality of flip-flops. ### Claim 18 (depends on 15) The display device of claim 15, wherein the operation unit performs AND operations on output signals supplied from at least two flip-flops among the plurality of flip-flops. ### Claim 19 (depends on 14) The display device of claim 14, wherein the image data signals have a horizontal synchronization start signal generation period and an effective image data period, the data driving circuit provides the respective data signals in the effective image data period using j bits of the image data signals, and the horizontal synchronization start signal generation circuit provides the horizontal synchronization start signal using k bits of the image data signals included in the horizontal synchronization start signal generation period, wherein j and k are natural numbers. ### Claim 20 (depends on 19) The display device of claim 19, wherein the horizontal synchronization start signal generation circuit generates the horizontal synchronization start signal when the k bits of the image data signals included in the horizontal synchronization start signal generation period are all at high levels.