# US 8,542,144 B2 · Analog to digital converter > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,542,144 B2 - Document ID: US8542144B2 - Status: Granted - Kind: B2 - Application number: 13/249,745 - Filed: 2011-09-30 - Published: 2013-04-04 - Granted: 2013-09-24 - Earliest claimed: 2011-09-30 - Assignees: Silicon Laboratories Inc. - Applicants: Abdulkerim L. Coban - Inventors: Abdulkerim L. Coban - Web page: https://patentgrep.com/patent/US8542144B2 ## CPC - H03M 1/20: Increasing resolution using an n bit system to obtain n + m bits - H03M 1/462: {Details of the control circuitry, e.g. of the successive approximation register} - H03M 1/76: using switching tree - H03M 1/765: {using a single level of switches which are controlled by unary decoded digital signals} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract An analog to digital converter converts an input analog signal to a digital representation using successive approximation logic to generate a plurality of digital values approximating the analog signal. Evaluation logic evaluates each of the digital values by converting each of the digital values in a digital to analog converter (DAC) to a DAC analog signal and comparing the DAC analog signal to the input analog signal to determine a comparison result used by the successive approximation logic to generate a next one of the digital values. An evaluation time period for one or more bits of the digital representation is longer than for one or more other bits in the digital representation. The DAC includes a resistor ladder. Reference voltages of the DAC are increased for evaluation of the least significant bit (LSB) to obtain more accurate results without increasing a number of resistors. ## Claims ### Claim 1 An analog to digital converter to convert an input analog signal to a digital representation comprising: successive approximation logic configured to successively generate a plurality of digital values approximating the analog signal; and evaluation logic to evaluate each of the digital values by converting each of the digital values in a digital to analog converter (DAC) to a DAC analog signal and compare the DAC analog signal to the input analog signal to determine a comparison result used by the successive approximation logic to generate a next one of the digital values; wherein an evaluation time period for one or more bits of the digital representation is shorter than for one or more other bits in the digital representation; and wherein the evaluation time period varies according to bit position, the evaluation time period of a most significant bit of the digital representation being longer than the evaluation time period of a least significant bit of the digital representation. ### Claim 2 (depends on 1) The analog to digital converter as recited in claim 1, wherein the evaluation logic comprises the digital to analog converter coupled to receive the digital values. ### Claim 3 (depends on 2) The analog to digital converter as recited in claim 2 further comprising: a comparator to compare the input analog signal to each of the DAC analog signals and supply the comparison result to the successive approximation logic to determine whether to increase or decrease a next digital value with respect to a current digital value. ### Claim 4 (depends on 2) The analog to digital converter as recited in claim 2 wherein the digital to analog converter comprises a resistor ladder. ### Claim 5 (depends on 4) The analog to digital converter as recited in claim 4 further comprising a first circuit to supply a first reference voltage at a first voltage value to the resistor ladder responsive to a first value of a least significant bit of the digital representation and to supply the first reference voltage at a second voltage value, different than the first voltage value, responsive to a second value of the least significant bit of the digital representation. ### Claim 6 (depends on 5) The analog to digital converter as recited in claim 5 wherein the second voltage value is higher than the first voltage value. ### Claim 7 (depends on 6) The analog to digital converter as recited in claim 6 wherein the second value of the least significant bit is a one. ### Claim 8 (depends on 5) The analog to digital converter as recited in claim 5 further comprising a second circuit to supply a second reference voltage at a third voltage value to the resistor ladder responsive to the first value of a least significant bit of the digital representation and to supply the second reference voltage at a fourth voltage value, different than the third voltage value, responsive to the second value of the least significant bit of the digital representation. ### Claim 9 A method for converting an analog signal to a digital representation comprising: generating successive digital values of the digital representation; and evaluating each of the successive digital values with respect to the analog signal using an evaluation time that varies, for at least some bits of the digital representation, according to a bit position of the digital representation being evaluated, the evaluation time being less for at least some less significant bits as compared to at least some more significant bits of the digital representation. ### Claim 10 (depends on 9) The method as recited in claim 9 further comprising: converting each of the digital values to respective analog signals. ### Claim 11 (depends on 10) The method as recited in claim 10 wherein the evaluating includes supplying each of the digital values to a digital to analog converter and generating analog voltages corresponding to respective ones of the digital values. ### Claim 12 (depends on 11) The method as recited in claim 11 further comprising: comparing the analog voltages to the analog signal to generate respective comparison results; and using respective ones of the comparison results to generate respective ones of the successive digital values. ### Claim 13 (depends on 11) The method as recited in claim 11 wherein the digital to analog converter includes a plurality of resistors formed as a resistor ladder. ### Claim 14 (depends on 9) The method as recited in claim 9 further comprising: using a first number of cycles of a clock signal to evaluate a most significant bit of the digital representation; and using a second number of cycles of the clock signal, to evaluate a least significant bit of the digital representation, the first number being larger than the second number. ### Claim 15 A method for converting an analog signal to a digital representation comprising: generating successive digital values of the digital representation; evaluating each of the successive digital values with respect to the analog signal, the evaluating including supplying each of the digital values to a digital to analog converter formed as a resistor ladder and generating analog voltages corresponding to respective ones of the digital representation; changing reference voltages supplied to the resistor ladder for evaluation of a least significant bit of the digital representation. ### Claim 16 (depends on 15) The method as recited in claim 15 further comprising changing a high reference voltage of the reference voltages to be V REFP + V REFP - V REFN 2 N , where VREFP is a value of the high reference voltage used to evaluate high order bits of the digital value and VREFN is a value of a low reference voltage used to evaluate the high order bits of the digital value. ### Claim 17 (depends on 16) The method as recited in claim 16 further comprising changing the value of the low reference voltage to be V REFN + V REFP - V REFN 2 N . ### Claim 18 (depends on 15) The method as recited in claim 15 further comprising evaluating each of the successive digital values with respect to the analog signal using an evaluation time that varies, for at least some bits of the digital representation, according to a bit position of the digital representation being evaluated. ### Claim 19 An analog to digital converter to convert an input analog signal to a digital representation comprising: successive approximation logic configured to successively generate a plurality of digital values corresponding to the analog signal to generate the digital representation; a digital to analog converter (DAC) to generate DAC signals corresponding to the digital values; a comparator to compare the DAC signals to the input analog signal and supply a comparison result to the successive approximation logic to generate a next one of digital values, wherein the DAC includes, a resistor ladder; and a first circuit to supply a first reference voltage at a first voltage value to the resistor ladder responsive to a first value of a least significant bit of the digital representation and to supply the first reference voltage at a second voltage value, different than the first voltage value, responsive to a second value of the least significant bit of the digital representation. ### Claim 20 (depends on 19) The analog to digital converter as recited in claim 19 wherein the second voltage value is higher than the first voltage value. ### Claim 21 (depends on 19) The analog to digital converter as recited in claim 19 wherein the second value of the least significant bit is a one. ### Claim 22 (depends on 19) The analog to digital converter as recited in claim 19 further comprising a second circuit to supply a second reference voltage at a third voltage value to the resistor ladder responsive to the first value of a least significant bit of the digital representation and to supply the second reference voltage at a fourth voltage value, different than the third voltage value, responsive to the second value of the least significant bit of the digital representation.