# US 8,542,143 B1 · Pipelined ADC stage filters > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,542,143 B1 - Document ID: US8542143B1 - Status: Granted - Kind: B1 - Application number: 13/413,430 - Filed: 2012-03-06 - Published: 2013-09-12 - Granted: 2013-09-24 - Earliest claimed: 2012-03-06 - Assignees: Crest Semiconductors, Inc. - Applicants: Yusuf Haque; Ryan James Kier; Rex K. Hales; Paul Talmage Watkins; Marcellus C. Harper - Inventors: Yusuf Haque; Ryan James Kier; Rex K. Hales; Paul Talmage Watkins; Marcellus C. Harper - Web page: https://patentgrep.com/patent/US8542143B1 ## CPC - H03M 1/0626: {by filtering} - H03M 1/1215: {using time-division multiplexing} - H03M 1/124: {Sampling or signal conditioning arrangements specially adapted for A/D converters} - H03M 1/164: {the steps being performed sequentially in series-connected stages (H03M1/161 takes precedence)} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract A pipelined Analog-to-Digital Converter (ADC) stage includes a main sampling path having a first filter in series with a first sample and hold circuit and a sub-ADC sampling path having a second filter in series with a second sample and hold circuit driving a sub-ADC connected to a sub-Digital-to-Analog Converter (DAC). The frequency response of the main sampling path is matched to a frequency response of the sub-ADC sampling path such that a residue signal of the pipelined ADC stage stays within range. ## Claims ### Claim 1 A pipelined Analog-to-Digital Converter (ADC) stage comprising: a main sampling path comprising a first filter in series with a first sample and hold circuit; and a sub-ADC sampling path comprising a second filter in series with a second sample and hold circuit driving a sub-ADC connected to a sub-Digital-to-Analog Converter (DAC); wherein a frequency response of said main sampling path is matched to a frequency response of said sub-ADC sampling path such that a residue signal of said pipelined ADC stage stays within range. ### Claim 2 (depends on 1) The pipelined ADC of claim 1, further comprising a signal input that is connected to multiple filters, said filters being connected to said main sampling path, said sub-ADC sampling path, and bootstrap circuitry, said bootstrap circuitry having outputs connected to said sample and hold circuits within said pipelined ADC stage. ### Claim 3 (depends on 2) The pipelined ADC of claim 2, wherein said bootstrap circuitry is shared by said first sample and hold circuit and said second sample and hold circuit. ### Claim 4 (depends on 2) The pipelined ADC of claim 2, wherein said first sample and hold circuit and said second sample and hold circuit utilize different bootstrap circuits. ### Claim 5 (depends on 1) The pipelined ADC of claim 1, wherein a frequency response of said sub-ADC is not matched with a frequency response of said main sampling path. ### Claim 6 (depends on 1) The pipelined ADC of claim 1, wherein said main sampling path is configured to sample an input signal in a time-interleaved manner. ### Claim 7 (depends on 3) The pipelined ADC of claim 3, wherein each sampling circuit of at least one of: said main sampling path and said sub-ADC sampling path uses a different filter. ### Claim 8 (depends on 1) The pipelined ADC of claim 1, wherein said pipelined ADC is a differential pipelined ADC. ### Claim 9 (depends on 1) The pipelined ADC of claim 1, wherein sampling of said main sampling path is performed using capacitors of said MDAC. ### Claim 10 (depends on 1) The pipelined ADC of claim 1, wherein said sampling of said sub-ADC sampling path is performed using capacitors of said sub-ADC. ### Claim 11 (depends on 1) The pipelined ADC of claim 1, wherein said filters are designed to mitigate an impact of charge injections from said sampling paths. ### Claim 12 (depends on 1) The pipelined ADC of claim 1, further comprising, bootstrap circuitry connected a sample-and-hold circuit within one of said sampling paths, said bootstrap circuitry utilizing a filter, said filter causing a path through said bootstrap circuitry to have a frequency response that matches said frequency response of said main sampling path. ### Claim 13 (depends on 1) The pipelined ADC of claim 1, wherein at least one of said filters comprises at least one of: differential components and single-ended components. ### Claim 14 A method for operating a pipelined Analog-to-Digital Converter (ADC) stage, the method comprising: sampling an input signal with a main sampling path comprising a first snubbing filter and a Multiplying-Digital-to-Analog Converter (MDAC); and sampling said input signal with a sub-ADC sampling path comprising a second filter and a sub-ADC connected to said MDAC; wherein a frequency response of said main sampling path is matched to a frequency response of said sub-ADC sampling path such that a residue signal of said pipelined ADC stage stays within range. ### Claim 15 (depends on 14) The method of claim 14, wherein a frequency response of said sub-ADC is not matched with a frequency response of said main sampling path. ### Claim 16 (depends on 14) The method of claim 14, wherein said main sampling path is configured to sample an input signal in a time-interleaved manner. ### Claim 17 (depends on 14) The method of claim 14, wherein said pipelined ADC is a differential pipelined ADC. ### Claim 18 (depends on 14) The method of claim 14, wherein sampling of said main sampling path is performed using capacitors of said MDAC. ### Claim 19 (depends on 14) The method of claim 14, wherein said sampling of said sub-ADC sampling path is performed using capacitors of said sub-ADC. ### Claim 20 A pipelined Analog-to-Digital Converter (ADC) comprising a number of stages, a first stage comprising: a signal input connected to a main sampling path comprising a first snubbing filter between said signal input and a Multiplying-Digital-to-Analog Converter (MDAC); and a sub-ADC sampling path comprising a second filter between said signal input and a sub ADC connected to said MDAC, said sub-ADC sampling path also connected to said signal input; wherein a frequency response of said main sampling path is matched to a frequency response of said sub-ADC sampling path such that a residue signal of said pipelined ADC stage stays within range and a frequency response of said sub-ADC is not matched with a frequency response of said main sampling path.