# US 8,542,073 B2 · Variable-capacitance device

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- Number: US 8,542,073 B2
- Document ID: US8542073B2
- Status: Granted
- Kind: B2
- Application number: 13/067,328
- Filed: 2011-05-25
- Published: 2011-12-22
- Granted: 2013-09-24
- Earliest claimed: 2010-06-22
- Assignees: Renesas Electronics Corporation
- Applicants: Tomokazu Matsuzaki; Kazutoshi Sako
- Inventors: Tomokazu Matsuzaki; Kazutoshi Sako
- Web page: https://patentgrep.com/patent/US8542073B2

## CPC

- H03K 3/354: Astable circuits
- H03K 3/017: Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015})
- H03K 5/133: using a chain of active delay devices
- H03L 7/089: the phase or frequency detector generating up-down pulses (H03L7/087 takes precedence)
- H03K 2005/00071: {by adding capacitance as a load}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

A variable-capacitance device includes a first capacitance element coupled between a first power supply terminal and an output terminal, a capacitance selection switch that is turned on and off in accordance with a capacitance switching signal, a second capacitance element coupled in parallel to the first capacitance element and in series to the capacitance selection switch, and an error correction circuit configured to operate such that in a state in which the capacitance selection switch is in an OFF state, in response to a charge reset signal that causes a voltage at the output terminal to be reset to a reset voltage, the error correction circuit substantially eliminates a difference between the voltage at the output terminal and a voltage at a capacitance switching node at which the second capacitance element is coupled to the capacitance selection switch.

## Claims

### Claim 1

A variable-capacitance device comprising:
a first capacitance element coupled between a first power supply terminal and an output terminal;
a capacitance selection switch configured to turn on or off in accordance with a capacitance switching signal;
a second capacitance element coupled in parallel to the first capacitance element and in series to the capacitance selection switch; and
an error correction circuit configured to operate such that in a state in which the capacitance selection switch is in an OFF state, in response to a charge reset signal that causes a voltage at the output terminal to be reset to a reset voltage, the error correction circuit substantially eliminates a difference between the voltage at the output terminal and a voltage at a capacitance switching node at which the second capacitance element is coupled to the capacitance selection switch,
wherein the error correction circuit includes:
a first switch circuit configured to apply a reset voltage to the capacitance switching node in response to the charge reset signal, wherein the reset voltage is supplied from a second power supply terminal; and
a second switch circuit coupled in series to the first switch circuit and configured to switch the first switch circuit between an enable state and a disable state wherein the second switch circuit is controlled exclusively with respect to the capacitance selection switch in terms of their ON state.

### Claim 2 (depends on 1)

The variable-capacitance device according to claim 1,
wherein the second capacitance element is coupled such that a first terminal thereof is coupled to the output terminal and a second terminal thereof is coupled to the capacitance switching node, and
wherein the capacitance selection switch is coupled such that a first terminal thereof is coupled to the capacitance switching node and a second terminal thereof is coupled to the first power supply terminal.

### Claim 3 (depends on 1)

The variable-capacitance device according to claim 1
wherein the second capacitance element is coupled such that a first terminal thereof is coupled to the capacitance switching node and a second terminal thereof is coupled to the first power supply terminal, and
wherein the capacitance selection switch is coupled such that a first terminal thereof is coupled to the output terminal and a second terminal thereof is coupled to the capacitance switching node.

### Claim 4 (depends on 1)

The variable-capacitance device according to claim 1, further comprising:
a reset circuit coupled between the output terminal and a second power supply terminal and configured to apply the reset voltage supplied from the second power supply terminal to the output terminal in response to the charge reset signal.

### Claim 5 (depends on 1)

The variable-capacitance device according to claim 1, further comprising:
a current source configured to charge or discharge the first capacitance element in response to a charge/discharge control signal whose enable state is controlled exclusively with respect to the charge reset signal.

### Claim 6 (depends on 1)

The variable-capacitance device according to claim 1, wherein the variable-capacitance device is used as a capacitance element in an oscillation circuit whose oscillation frequency is set by a constant current set by resistance and capacitance of the capacitance element.

### Claim 7

A variable-capacitance device comprising:
a first capacitance element coupled between a first power supply terminal and an output terminal;
a capacitance selection switch configured to turn on or off in accordance with a capacitance switching signal;
a second capacitance element coupled in parallel to the first capacitance element and in series to the capacitance selection switch; and
an error correction circuit configured to operate such that in a state in which the capacitance selection switch is in an OFF state, in response to a charge reset signal that causes a voltage at the output terminal to be reset to a reset voltage, the error correction circuit substantially eliminates a difference between the voltage at the output terminal and a voltage at a capacitance switching node at which the second capacitance element is coupled to the capacitance selection switch,
wherein the variable-capacitance device is used as a capacitance element in an oscillation circuit whose oscillation frequency is set by a constant current set by resistance and capacitance of the capacitance element, and
wherein the oscillation circuit includes:
a filter capacitor configured to generate an oscillation frequency control voltage depending on the amount of a charge stored in the filter capacitor based on an oscillation frequency setting current;
an oscillator configured to output an oscillation signal with a frequency varying according to the oscillation frequency control voltage;
a control circuit configured to generate a timing control signal with a logical level that is switched based on the period of the oscillation signal;
a frequency detection circuit including the variable-capacitance device and configured to generate a frequency detection voltage with a voltage level varying according to the length of the period of the oscillation signal and a charging/discharging current of the variable-capacitance device based on the timing control signal; and
a differential amplifier configured to continuously changing the oscillation frequency setting current according to a voltage difference between the frequency detection voltage and a reference voltage and output the resultant oscillation frequency setting current to the filter capacitor.

### Claim 8 (depends on 1)

The variable-capacitance device according to claim 1, wherein the variable-capacitance device is used in a time constant circuit that sets a delay time of an output signal with respect to an input signal.