# US 8,542,068 B2 · Oscillator with highly-adjustable bang-bang control

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- Number: US 8,542,068 B2
- Document ID: US8542068B2
- Status: Granted
- Kind: B2
- Application number: 13/332,990
- Filed: 2011-12-21
- Published: 2013-06-27
- Granted: 2013-09-24
- Earliest claimed: 2011-12-21
- Assignees: Advanced Micro Devices, Inc.
- Applicants: Bruce A. Doyle; Emerson S. Fang; Alvin L. Loke; Shawn Searles; Stephen F. Greenwood
- Inventors: Bruce A. Doyle; Emerson S. Fang; Alvin L. Loke; Shawn Searles; Stephen F. Greenwood
- Web page: https://patentgrep.com/patent/US8542068B2

## CPC

- H03L 7/0807: {concerning mainly a recovery circuit for the reference signal}
- H03K 3/0322: {with differential cells}
- H03L 7/087: using at least two phase detectors or a frequency and phase detector in the loop
- H03L 7/0995: {the oscillator comprising a ring oscillator}
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A device may include an oscillator to generate a clock signal based on first and second control signals. The oscillator may include a first buffer stage a second buffer stage. The first buffer stage may output a first signal that is based on an output of the second buffer stage and the first control signal. The second buffer stage may output the clock signal. The clock signal may be based on the first signal and the second control signal.

## Claims

### Claim 1

A device comprising:
an oscillator to generate a first clock signal based on a first control signal and a second control signal,
the oscillator comprising:
a first buffer stage, and
a second buffer stage,
the first buffer stage to:
output a signal that is based on an output of the second buffer stage and the first control signal,
the second buffer stage to:
output the first clock signal,
the first clock signal being based on the first signal, output by the first buffer stage, and the second control signal; and
one or more components to:
receive a second clock signal that indicates data edges of a data stream, and
generate the first control signal and the second control signal based on the second clock signal.

### Claim 2 (depends on 1)

The device of claim 1, where a phase associated with the first clock signal is a same phase as a phase associated with the second clock signal.

### Claim 3 (depends on 1)

The device of claim 1, where each of the first buffer stage and the second buffer stage includes at least one pair of buffers.

### Claim 4 (depends on 1)

The device of claim 1, where each of the first buffer stage and the second buffer stage includes at least one pair of inverters.

### Claim 5 (depends on 1)

The device of claim 1, where the signal output by the first buffer stage corresponds to a first signal,
where the oscillator further includes:
a third buffer stage to:
receive a third control signal that is a same signal as one of the first control signal or the second control signal,
receive a second signal that is based on an output of the second buffer stage, and
output a third signal based on the third control signal and the second signal.

### Claim 6 (depends on 1)

The device of claim 1, where a phase associated with the first clock signal is not a complement of a phase associated with the output of the second buffer stage.

### Claim 7 (depends on 1)

The device of claim 1, where a phase associated with the first clock signal is a complement of a phase associated with the output of the second buffer stage.

### Claim 8 (depends on 1)

The device of claim 1, where the first control signal and the second control signal are supplied by a first current source and a second current source, respectively.

### Claim 9 (depends on 1)

The device of claim 1, where the first control signal and the second control signal are supplied by a first voltage source and a second voltage source, respectively.

### Claim 10 (depends on 1)

The device of claim 1, where each rising edge of the first clock signal indicates a time at which the data stream is to be sampled.

### Claim 11

A system comprising:
a clock generation component to generate a first clock signal based on a first control signal and a second control signal,
the clock generation component comprising:
a first buffer stage, and
a second buffer stage,
the first buffer stage to:
output a signal that is based on an output of the second buffer stage and the first control signal,
the second buffer stage to:
output the first clock signal,
the first clock signal being based on the signal, output by the first buffer stage, and the second control signal; and
one or more detector components to:
generate the first control signal and the second control signal based on a second clock signal that indicates data edges of a data stream.

### Claim 12 (depends on 11)

The system of claim 11, where the signal output by the first buffer stage corresponds to a first signal, and
where the clock generation component further includes:
a third buffer stage to output a second signal based on:
a third control signal that is a same signal as one of the first control signal or the second control signal, and
a third signal that is based on the output of the second buffer stage.

### Claim 13 (depends on 11)

The system of claim 11, where a phase associated with the first clock signal is not a complement of a phase associated with the output of the second buffer stage.

### Claim 14 (depends on 11)

The system of claim 11, where a phase associated with the first clock signal is a complement of a phase associated with the output of the second buffer stage.

### Claim 15 (depends on 11)

The system of claim 11, where the one or more detector components include one or more current sources that supply the first control signal and the second control signal.

### Claim 16 (depends on 11)

The system of claim 11, where the one or more detector components include one or more voltage sources that supply the first control signal and the second control signal.

### Claim 17 (depends on 11)

The system of claim 11, where a phase associated with the first clock signal is a same phase as a phase associated with the second clock signal, and
where each rising edge of the first clock signal indicates a time at which the data stream is to be sampled.

### Claim 18

A method, comprising:
outputting, by a first buffer stage of an oscillator device, a signal that is based on an output of a second buffer stage of the oscillator device and a first control signal;
receiving, by the second buffer stage, the signal output by the first buffer stage; and
outputting, by the second buffer stage, a first clock signal that is based on:
the signal output by the first buffer stage, and
a second control signal that is different from the first control signal,
the first control signal and the second control signal being generated based on a second clock signal that indicates data edges of a data stream,
the first clock signal indicating a time at which the data stream is to be sampled.

### Claim 19 (depends on 18)

The method of claim 18, further comprising:
receiving, by a detector component associated with the oscillator device, the second clock signal; and
generating, by the detector component, the first control signal and the second control signal based on the second clock signal.

### Claim 20 (depends on 18)

The method of claim 18, where the signal output by the first buffer signal corresponds to a first signal,
the method further comprising:
receiving, by a third buffer stage of the oscillator device, a third control signal that is a same signal as one of the first control signal or the second control signal,
receiving, by the third buffer stage, a second signal that is based on the output of the second buffer stage, and
outputting, by the third buffer stage, a third signal based on the third control signal and the second signal.