# US 8,542,045 B2 · Duty correcting circuit, delay-locked loop circuit and method of correcting duty > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,542,045 B2 - Document ID: US8542045B2 - Status: Granted - Kind: B2 - Application number: 13/078,151 - Filed: 2011-04-01 - Published: 2011-12-08 - Granted: 2013-09-24 - Earliest claimed: 2010-06-07 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Tae-Sik Na; Jun-Bae Kim - Inventors: Tae-Sik Na; Jun-Bae Kim - Web page: https://patentgrep.com/patent/US8542045B2 ## CPC - H03K 5/1565: {the output pulses having a constant duty cycle} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract The duty correcting circuit includes a duty cycle corrector, a duty detector and a duty correction code generator. The duty cycle corrector corrects a duty cycle of an input clock signal to generate an output clock signal. The duty detector adjusts a delay time of the output clock signal to generate a sampling clock signal, samples the output clock signal in response to the sampling clock signal to generate sample data, and detects a duty of the output clock signal based on logic states of the sample data. Therefore, the duty correcting circuit precisely detects and corrects a duty of the output clock signal. ## Claims ### Claim 1 A duty correcting circuit comprising: a duty cycle corrector configured to correct a duty cycle of an input clock signal in response to a duty correction code to generate an output clock signal; a duty detector configured to, adjust a delay time of the output clock signal to generate a sampling clock signal, sample the output clock signal in response to the sampling clock signal, generate first sample data and second sample data, and detect a duty of the output clock signal based on logic states of the first sample data and the second sample data to generate a duty-up signal and a duty-down signal; and a duty correction code generator configured to generate the duty correction code in response to the duty-up signal and the duty-down signal, wherein the duty detector is configured to adjust the delay time of the output clock signal based on the logic states of the first and second sample data. ### Claim 2 (depends on 1) The circuit of claim 1, wherein the duty detector comprises: a phase splitter configured to split a phase of the output clock signal to generate a first clock signal and a second clock signal, the second clock signal having a phase difference of 180 degrees from the first clock signal; a first delay circuit configured to, adjust a delay amount in response to a delay-up signal and a delay-down signal, and delay the first clock signal to generate a third clock signal; a second delay circuit configured to, adjust a delay amount in response to the delay-up signal and the delay-down signal, and delay the second clock signal to generate a fourth clock signal; a first flip-flop configured to sample the first clock signal in response to the third clock signal to generate the first sample data; a second flip-flop configured to sample the second clock signal in response to the fourth clock signal to generate the second sample data; and a control circuit configured to detect the duty of the output clock signal based on logic states of the first sample data and the second sample data to generate the delay-up signal, the delay-down signal, the duty-up signal and the duty-down signal. ### Claim 3 (depends on 2) The circuit of claim 2, wherein the duty detector is configured to, generate the delay-up signal to increase the delay time of the output clock signal if the first sample data and the second sample data are enabled, and generate the delay-down signal to decrease the delay time of the output clock signal if the first sample data and the second sample data are disabled. ### Claim 4 (depends on 2) The circuit of claim 2, wherein the duty detector is configured to generate the duty-up signal to increase the duty of the output clock signal if the first sample data is disabled and the second sample data is enabled. ### Claim 5 (depends on 2) The circuit of claim 2, wherein the duty detector is configured to generate the duty-down signal to decrease the duty of the output clock signal if the first sample data is enabled and the second sample data is disabled. ### Claim 6 (depends on 1) The circuit of claim 1, wherein the duty detector comprises: a phase splitter configured to split a phase of the output clock signal to generate a first clock signal and a second clock signal, the first clock signal and the second clock signal having different phases; a delay circuit configured to, adjust a delay amount in response to a delay-up signal and a delay-down signal, and delay the first clock signal to generate a third clock signal based on the delay amount; a first flip-flop configured to sample the first clock signal in response to a rising edge of the third clock signal to generate the first sample data; a second flip-flop configured to sample the second clock signal in response to a falling edge of the third clock signal to generate the second sample data; and a control circuit configured to detect the duty of the output clock signal based on logic states of the first sample data and the second sample data to generate the delay-up signal, the delay-down signal, the duty-up signal and the duty-down signal. ### Claim 7 (depends on 1) The circuit of claim 1, wherein the duty detector comprises: a first phase splitter configured to split a phase of the output clock signal to generate a first clock signal and a second clock signal, the first clock signal and the second clock signal having different phases; a delay circuit configured to, adjust a delay amount in response to a delay-up signal and a delay-down signal, and delay the first clock signal based on the delay amount; a second phase splitter configured to split a phase of an output signal of the delay circuit to generate a third clock signal and a fourth clock signal, the third clock signal and the fourth clock signal having a phase difference of 180 degrees from each other; a first flip-flop configured to sample the first clock signal in response to the third clock signal to generate the first sample data; a second flip-flop configured to sample the second clock signal in response to the fourth clock signal to generate the second sample data; and a control circuit configured to detect the duty of the output clock signal based on logic states of the first sample data and the second sample data to generate the delay-up signal, the delay-down signal, the duty-up signal and the duty-down signal. ### Claim 8 A duty correcting circuit comprising: a duty cycle corrector configured to correct a duty cycle of an input clock signal in response to a duty-up signal and a duty-down signal to generate an output clock signal; and a duty detector configured to, delay the output clock signal to generate a delayed output clock signal, invert a phase of the delayed output clock signal to generate an inverted and delayed output clock signal, synchronize the output clock signal to the inverted and delayed output clock signal, sample the output clock signal in response to the inverted and delayed output clock signal to generate first sample data and second sample data, and detect a duty of the output clock signal based on logic states of the first sample data and the second sample data to generate the duty-up signal and the duty-down signal. ### Claim 9 (depends on 8) The circuit of claim 8, wherein the duty detector is configured to adjust a delay time of the output clock signal based on a logic state of the first sample data which is the output clock signal sampled at a rising edge of the inverted and delayed output clock signal, and the duty detector is configured to detect a duty of the output clock signal based on a logic state of the second sample data which is the output clock signal sampled at a falling edge of the inverted and delayed output clock signal. ### Claim 10 (depends on 8) The circuit of claim 8, wherein the duty detector is configured to adjust the delay time of the output clock signal using a delay line of a delay-locked-loop circuit. ### Claim 11 (depends on 8) The circuit of claim 8, wherein the duty detector comprises: a delay circuit configured to delay the output clock signal in response to a delay-up signal and a delay-down signal to generate the delayed output clock signal; an inverter configured to invert the delayed output clock signal to generate the inverted and delayed output clock signal; a first flip-flop configured to sample the output clock signal in response to a falling edge of the inverted and delayed output clock signal to generate the first sample data; a second flip-flop configured to sample the output clock signal in response to a rising edge of the inverted and delayed output clock signal to generate the second sample data; and a control circuit configured to generate the delay-up signal, the delay-down signal, the duty-up signal and the duty-down signal based on logic states of the first sample data and the second sample data. ### Claim 12 (depends on 11) The circuit of claim 11, wherein the duty detector is configured to generate the delay-up signal to increase the delay time of the output clock signal if the second sample data has a first logic state, and the duty detector is configured to generate the delay-down signal to decrease the delay time of the output clock signal if the second sample data has a second logic state. ### Claim 13 (depends on 11) The circuit of claim 11, wherein the duty detector is configured to generate the duty-up signal to increase the duty of the output clock signal if an output enable signal is enabled and the first sample data has a first logic state, and the duty detector is configured to generate the duty-down signal to decrease the duty of the output clock signal if the output enable signal is enabled and the first sample data has a second logic state. ### Claim 14 (depends on 11) The circuit of claim 11, wherein the duty correcting circuit further comprises a duty correction code generator configured to generate a duty correction code in response to the duty-up signal and the duty-down signal and provide the duty correction code to the duty cycle corrector. ### Claim 15 A duty correcting circuit comprising: a duty cycle corrector configured to generate an output clock signal based on a duty correction code; a duty detector configured to, detect a duty of the output clock signal based on logic states associated with sampled data, generate a duty-up signal and a duty-down signal based on the detected duty; and a duty correction code generator configured to generate the duty correction code based on the duty-up signal and the duty-down signal, wherein the duty detector includes, a delay circuit configured to, adjust a delay amount based on a delay-up signal and a delay-down signal, and generate another clock signal based on the delay amount and a phase of the output clock signal. ### Claim 16 (depends on 15) The circuit of claim 15, wherein the duty detector comprises: a phase splitter configured to generate a first clock signal and a second clock signal based on a phase of the output clock signal, the second clock signal having a phase difference of 180 degrees from the first clock signal. ### Claim 17 (depends on 15) The circuit of claim 15, wherein the duty detector comprises: one or more flip-flops configured to generate the sampled data based on the another clock signal. ### Claim 18 (depends on 17) The circuit of claim 17, wherein the duty detector comprises: a control circuit configured to generate the delay-up signal, the delay-down signal, the duty-up signal and the duty-down signal based on the output clock and the logic states associated with the sampled data.