# US 8,542,044 B2 · Semiconductor integrated circuit and method for driving the same

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- Number: US 8,542,044 B2
- Document ID: US8542044B2
- Status: Granted
- Kind: B2
- Application number: 13/334,241
- Filed: 2011-12-22
- Published: 2013-04-25
- Granted: 2013-09-24
- Earliest claimed: 2011-10-20
- Assignees: Hynix Semiconductor Inc.
- Applicants: Yong-Ju Kim; Dae-Han Kwon; Hae-Rang Choi; Jae-Min Jang
- Inventors: Yong-Ju Kim; Dae-Han Kwon; Hae-Rang Choi; Jae-Min Jang
- Web page: https://patentgrep.com/patent/US8542044B2

## CPC

- H03L 7/0814: {the phase shifting device being digitally controlled}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 29/023: {in clock generator or timing circuitry}
- H03L 7/0816: {the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input}
- G11C 11/40: using transistors
- G11C 2029/0409: {Online test}
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A semiconductor integrated circuit includes: a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a source clock signal by a first delay time for obtaining a lock, wherein an update period of the DLL is controlled in response to an update period control signal after locking is completed; and an update period controller configured to generate the update period control signal based on a second delay time occurring in a loop path of the DLL in response to the source clock signal and a plurality of control signals provided from the DLL.

## Claims

### Claim 1

A semiconductor integrated circuit comprising:
a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a source clock signal by a first delay time for obtaining a lock, wherein an update period of the DLL is controlled in response to an update period control signal after locking is completed; and
an update period controller configured to generate the update period control signal based on a second delay time occurring in a loop path of the DLL in response to the source clock signal and a plurality of control signals provided from the DLL.

### Claim 2 (depends on 1)

The semiconductor integrated circuit of claim 1, wherein the DLL comprises:
a first delay line configured to delay the source clock signal by the first delay line in response to a delay control signal and output the DLL clock signal;
a first replica delay configured to delay the DLL clock signal by a third delay time equal to a delay through a clock path and output a feedback clock signal;
a first signal generation unit configured to generate a clock phase comparison signal and a locking completion signal in response to the source clock signal and the feedback clock signal; and
a second signal generation unit configured to generate the delay control signal in response to the clock phase comparison signal and the update period control signal.

### Claim 3 (depends on 2)

The semiconductor integrated circuit of claim 2, wherein the plurality of control signals comprise the delay control signal and the locking completion signal.

### Claim 4 (depends on 2)

The semiconductor integrated circuit of claim 2, wherein the second delay time comprises the first delay time and the third delay time.

### Claim 5 (depends on 2)

The semiconductor integrated circuit of claim 2, wherein the first signal generation unit comprises:
a phase comparison section configured to compare phases of the source clock signal and the feedback clock signal and output the clock phase comparison signal based on the phrase comparison; and
an edge detection section configured to output the locking completion signal in response to the clock phase comparison signal.

### Claim 6 (depends on 2)

The semiconductor integrated circuit of claim 2, wherein the second signal generation unit comprises a filter configured to filter the clock phase comparison signal.

### Claim 7 (depends on 4)

The semiconductor integrated circuit of claim 4, wherein the update period controller comprises:
a third signal generation unit configured to generate a synchronized locking completion signal and the update period control signal in response to the source clock signal, the locking completion signal, and a delayed locking completion signal; and
a fourth signal generation unit configured to delay the synchronized locking completion signal by the second delay time or a part of the second delay time and generate the delayed locking completion signal.

### Claim 8 (depends on 7)

The semiconductor integrated circuit of claim 7, wherein the fourth signal generation unit comprises:
a second delay line configured to delay the synchronized locking completion signal by the first delay time; and
a second replica delay configured to delay an output signal of the second delay line by the third delay time and output the delayed locking completion signal.

### Claim 9 (depends on 7)

The semiconductor integrated circuit of claim 7, wherein the third signal generation unit comprises:
a synchronization section configured to synchronize the locking completion signal with the source clock signal and output the synchronized locking completion signal;
an enable signal generation section configured to generate an enable signal in response to the synchronized locking completion signal and the delayed locking completion signal; and
an output section configured to output the update period control signal in response to the enable signal and the source clock signal.

### Claim 10 (depends on 9)

The semiconductor integrated circuit of claim 9, wherein the synchronization section and the enable signal generation section comprise a D flip-flop.

### Claim 11 (depends on 9)

The semiconductor integrated circuit of claim 9, wherein the output section comprises:
an output limiter configured to output the source clock signal during a period that the enable signal is activated; and
a counter configured to count the source clock signal outputted from the output limiter.

### Claim 12 (depends on 11)

The semiconductor integrated circuit of claim 11, wherein the output section further comprises an adder configured to add a first value to a counted value outputted from a counter and output the update period control signal.

### Claim 13 (depends on 11)

The semiconductor integrated circuit of claim 11, wherein the output limiter comprises an AND gate configured to perform an AND operation on the enable signal and the source clock signal.

### Claim 14 (depends on 2)

The semiconductor integrated circuit of claim 2, further comprising:
an input buffer configured to buffer an external clock signal and generate the source clock signal; and
an output driver configured to output data in synchronization with the DLL clock signal.

### Claim 15 (depends on 14)

The semiconductor integrated circuit of claim 14, wherein the third delay time comprises a delay time equal to a delay through a clock input path including the input buffer and a delay time equal to a delay through a clock output path including the output driver.

### Claim 16

A method for driving a semiconductor integrated circuit which includes a DLL configured to generate a DLL clock signal by delaying a source clock by a first delay time for obtaining a lock and an update period controller configured to control an update period of the DLL, the method comprising:
generating, by the DLL, the DLL clock signal by delaying a source clock signal by the first delay time, wherein the first delay time is variably controlled;
controlling, by the update period controller, the update period based on a second delay time that occurs in a loop path of the DLL in a state in which the generating of the DLL dock signal is completed; and
performing, by the DLL, an update in response to the controlled update period.

### Claim 17 (depends on 16)

The method of claim 16, wherein the second delay time comprises the first delay time and a third delay time equal to a delay through a clock path.

### Claim 18 (depends on 16)

The method of claim 16, wherein the controlling of the update period comprises:
activating, by the DLL, a locking completion signal as the generating of the DLL clock signal is completed;
counting, by the update period controller, the source clock signal during the second delay time and outputting the counted value, as the locking completion signal is activated; and
performing, by the DLL, an update in response to the update period controlled according to the counted value.

### Claim 19 (depends on 18)

The method of claim 18, wherein the outputting of the counted value comprises:
synchronizing the locking completion signal with the source clock signal and generating the synchronized locking completion signal;
generating a delayed locking completion signal by delaying the synchronized locking completion signal by the second delay time and generating an enable signal having an activation period in response to the synchronized locking completion signal and the delayed locking completion signal; and
counting the toggling number of the source clock signal during the activation period of the enable signal.

### Claim 20 (depends on 18)

The method of claim 18, wherein the outputting of the counted value comprises:
adding a first value to the counted value.