# US 8,542,042 B1 · Phase-locked loop architecture and clock distribution system

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- Number: US 8,542,042 B1
- Document ID: US8542042B1
- Status: Granted
- Kind: B1
- Application number: 13/532,528
- Filed: 2012-06-25
- Granted: 2013-09-24
- Earliest claimed: 2010-03-03
- Assignees: Altera Corporation
- Applicants: Tien Duc Pham; Sergey Shumarayev; Richard G. Cliff
- Inventors: Tien Duc Pham; Sergey Shumarayev; Richard G. Cliff
- Web page: https://patentgrep.com/patent/US8542042B1

## CPC

- H03L 7/23: with pulse counters or frequency dividers
- G06F 1/10: Distribution of clock signals {, e.g. skew}
- H03L 7/0807: {concerning mainly a recovery circuit for the reference signal}
- H03L 7/183: a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number {(H03L7/1806 takes precedence)}
- H03L 7/197: a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division {(H03L7/1806 takes precedence)}
- H04L 7/0331: {with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence)}
- H03L 7/1974: {for fractional frequency division}
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

One embodiment relates to a fracture-able PLL circuit. The fracture-able PLL circuit includes a first phase-locked loop circuit generating a first frequency output, a second phase-locked loop circuit; arranged to generate a second frequency output, and a plurality of shared output resources. Reconfigurable circuitry is arranged so that either of the first and second frequency outputs is receivable by each of the plurality of shared output resources. Another embodiment relates to an integrated circuit which includes a plurality of PMA modules, a plurality of multiple-purpose PLL circuits, and a programmable clock network. The programmable clock network is arranged to allow the clock signals output by the multiple-purpose PLL circuits to be selectively used either by the PMA modules for a transceiver application or by other circuitry for a non-transceiver application. Other embodiments and features are also disclosed.

## Claims

### Claim 1

An integrated circuit comprising:
a plurality of physical media attachment (PMA) modules, each PMA module including a plurality of clock data recovery (CDR) circuits which are arranged to receive a plurality of serial data signals and to output data from those signals in parallel form;
a plurality of multiple-purpose phase-locked loop (PLL) circuits; and
a programmable clock network which is arranged to allow the clock signals output by the multiple-purpose PLL circuits to be selectively used either by the PMA modules for a transceiver application or by other circuitry for a non-transceiver application.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein each PMA module is a PMA triplet module having three CDR circuits to support three serial data channels.

### Claim 3 (depends on 2)

The integrated circuit of claim 2, wherein each PMA triplet module has an adjacent multiple-purpose PLL circuit.

### Claim 4 (depends on 3)

The integrated circuit of claim 3, further comprising:
circuitry arranged such that each pair of multiple-purpose PLL circuits forms a fracture-able PLL circuit.

### Claim 5 (depends on 1)

The integrated circuit of claim 1, wherein use by a PMA module of a clock signal output by a multiple-purpose PLL circuit allows the PMA module to support an additional independent channel.

### Claim 6 (depends on 5)

The integrated circuit of claim 5, wherein the multiple-purpose PLL circuits include a voltage-controlled oscillator with an operating frequency sufficiently high to support a 3.75 Gbps data rate.