# US 8,542,034 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,542,034 B2 - Document ID: US8542034B2 - Status: Granted - Kind: B2 - Application number: 13/472,979 - Filed: 2012-05-16 - Published: 2012-11-22 - Granted: 2013-09-24 - Earliest claimed: 2011-05-20 - Assignees: Semiconductor Energy Laboratory Co., Ltd. - Applicants: Kiyoshi Kato - Inventors: Kiyoshi Kato - Web page: https://patentgrep.com/patent/US8542034B2 ## CPC - H03K 19/0013: {in field effect transistor circuits} - H03K 19/0944: using MOSFET {or insulated gate field-effect transistors, i.e. IGFET}(H03K19/096 takes precedence) - H10D 86/00: Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates - H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO} - H10D 86/60: wherein the TFTs are in active matrices - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract As semiconductor devices including semiconductors, logic circuits are given. Logic circuits include dynamic logic circuits and static logic circuits and are formed using transistors and the like. Dynamic logic circuits can store data for a certain period of time. Thus, leakage current from transistors causes more severe problems in dynamic logic circuits than in static logic circuits. A logic circuit includes a first transistor whose off-state current is small and a second transistor whose gate is electrically connected to the first transistor. Electric charge is supplied to a node of the gate of the second transistor through the first transistor. Electric charge is supplied to the node through a first capacitor and a second capacitor. On/off of the second transistor is controlled depending on a state of the electric charge. The first transistor includes an oxide semiconductor in a channel formation region. ## Claims ### Claim 1 A semiconductor device comprising: a first capacitor; a second capacitor; a first transistor; and a second transistor, wherein one electrode of the first capacitor and one electrode of the second capacitor are electrically connected to each other, wherein the one electrode of the first capacitor is electrically connected to a gate electrode of the second transistor, wherein the one electrode of the second capacitor is electrically connected to one of a source electrode and a drain electrode of the first transistor, and wherein a channel formation region of the first transistor comprises an oxide semiconductor. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the second transistor is an n-type channel transistor. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the second transistor is a p-type channel transistor. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein a node electrically connected to the gate electrode of the second transistor has electric charge, wherein a first signal is input to the gate electrode of the second transistor through the first capacitor, wherein a second signal is input to the gate electrode of the second transistor through the second capacitor, and wherein the electric charge, the first signal and the second signal are configured to control a switching function of the second transistor. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the semiconductor device is configured to be dynamically reconfigured. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein the oxide semiconductor comprises indium and zinc. ### Claim 7 A semiconductor device comprising: a first capacitor; a second capacitor; a first transistor; a second transistor; a third transistor; a fourth transistor; and an inverter, wherein one electrode of the first capacitor and one electrode of the second capacitor are electrically connected to each other, wherein the one electrode of the first capacitor is electrically connected to a gate electrode of the second transistor, wherein the one electrode of the second capacitor is electrically connected to one of a source electrode and a drain electrode of the first transistor, wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to one of a source electrode and a drain electrode of the third transistor, and wherein the other of the source electrode and the drain electrode of the third transistor is electrically connected to one of a source electrode and a drain electrode of the fourth transistor and the inverter. ### Claim 8 (depends on 7) The semiconductor device according to claim 7, wherein the first transistor comprises an oxide semiconductor. ### Claim 9 (depends on 7) The semiconductor device according to claim 7, wherein at least one of the third transistor and the fourth transistor comprises an oxide semiconductor. ### Claim 10 (depends on 7) The semiconductor device according to claim 7, wherein the second transistor is an n-type channel transistor. ### Claim 11 (depends on 7) The semiconductor device according to claim 7, wherein the second transistor is a p-type channel transistor. ### Claim 12 (depends on 7) The semiconductor device according to claim 7, wherein a node electrically connected to the gate electrode of the second transistor has electric charge, wherein a first signal is input to the gate electrode of the second transistor through the first capacitor, wherein a second signal is input to the gate electrode of the second transistor through the second capacitor, and wherein the electric charge, the first signal and the second signal are configured to control a switching function of the second transistor. ### Claim 13 (depends on 12) The semiconductor device according to claim 12, wherein a logical operation is output from the inverter, wherein the logical operation is a logical conjunction when the electric charge is in a first condition, and wherein the logical operation is a logical disjunction when the electric charge is in a second condition. ### Claim 14 (depends on 13) The semiconductor device according to claim 13, wherein the first signal and the second signal are high potentials in the first condition, and wherein the first signal and the second signal are low potentials in the second condition. ### Claim 15 (depends on 7) The semiconductor device according to claim 7, wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to a high potential power source, and wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to a low potential power source. ### Claim 16 (depends on 7) The semiconductor device according to claim 7, wherein the semiconductor device is configured to be dynamically reconfigured. ### Claim 17 A method for driving a semiconductor device, the semiconductor device comprising a first capacitor, a second capacitor, a first transistor; and a second transistor, wherein one electrode of the first capacitor and one electrode of the second capacitor are electrically connected to each other, wherein the one electrode of the first capacitor is electrically connected to a gate electrode of the second transistor, and wherein the one electrode of the second capacitor is electrically connected to one of a source electrode and a drain electrode of the first transistor, the method comprising the steps of: turning on the first transistor; turning off the first transistor to hold electric charge of a node electrically connected to the gate electrode of the second transistor; supplying a first signal to the gate electrode of the second transistor through the first capacitor; supplying a second signal to the gate electrode of the second transistor through the second capacitor; and controlling a switching function of the second transistor by the electric charge, the first signal and the second signal. ### Claim 18 (depends on 17) The method for driving a semiconductor device according to claim 17, wherein the first transistor comprises an oxide semiconductor. ### Claim 19 (depends on 17) The method for driving a semiconductor device according to claim 17, wherein the second transistor is an n-type channel transistor. ### Claim 20 (depends on 17) The method for driving a semiconductor device according to claim 17, wherein the second transistor is a p-type channel transistor. ### Claim 21 (depends on 17) The method for driving a semiconductor device according to claim 17, wherein the semiconductor device is configured to be dynamically reconfigured. ### Claim 22 A method for driving a semiconductor device, the semiconductor device comprising a first capacitor, a second capacitor, a first transistor; a second transistor, a third transistor, a fourth transistor and an inverter, wherein one electrode of the first capacitor and one electrode of the second capacitor are electrically connected to each other, wherein the one electrode of the first capacitor is electrically connected to a gate electrode of the second transistor, wherein the one electrode of the second capacitor is electrically connected to one of a source electrode and a drain electrode of the first transistor, wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to one of a source electrode and a drain electrode of the third transistor, and wherein the other of the source electrode and the drain electrode of the third transistor is electrically connected to one of a source electrode and a drain electrode of the fourth transistor and the inverter, the method comprising the steps of: turning on the first transistor; turning off the first transistor to hold electric charge of a node electrically connected to the gate electrode of the second transistor; supplying a first signal to the gate electrode of the second transistor through the first capacitor; supplying a second signal to the gate electrode of the second transistor through the second capacitor; controlling a switching function of the second transistor by the electric charge, the first signal and the second signal; and outputting a logical operation from the inverter. ### Claim 23 (depends on 22) The method for driving a semiconductor device according to claim 22, wherein the first transistor comprises an oxide semiconductor. ### Claim 24 (depends on 22) The method for driving a semiconductor device according to claim 22, wherein at least one of the third transistor and the fourth transistor comprises an oxide semiconductor. ### Claim 25 (depends on 22) The method for driving a semiconductor device according to claim 22, wherein the second transistor is an n-type channel transistor. ### Claim 26 (depends on 22) The method for driving a semiconductor device according to claim 22, wherein the second transistor is a p-type channel transistor. ### Claim 27 (depends on 22) The method for driving a semiconductor device according to claim 22, wherein the semiconductor device is configured to be dynamically reconfigured. ### Claim 28 (depends on 22) The method for driving a semiconductor device according to claim 22, wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to a high potential power source, and wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to a low potential power source. ### Claim 29 (depends on 22) The method for driving a semiconductor device according to claim 22, wherein the logical operation is a logical conjunction when the electric charge is in a first condition, and wherein the logical operation is a logical disjunction when the electric charge is in a second condition. ### Claim 30 (depends on 29) The method for driving a semiconductor device according to claim 29, wherein the first signal and the second signal are high potentials in the first condition, and wherein the first signal and the second signal are low potentials in the second condition.