# US 8,542,032 B1 · Integrated circuits with interconnect selection circuitry > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,542,032 B1 - Document ID: US8542032B1 - Status: Granted - Kind: B1 - Application number: 13/345,436 - Filed: 2012-01-06 - Granted: 2013-09-24 - Earliest claimed: 2012-01-06 - Assignees: Altera Corporation - Applicants: Michael D. Hutton; Irfan Rahim - Inventors: Michael D. Hutton; Irfan Rahim - Web page: https://patentgrep.com/patent/US8542032B1 ## CPC - G06F 30/347: Physical level, e.g. placement or routing - G06F 30/3312: Timing analysis - G06F 30/3315: using static timing analysis [STA] - G06F 30/34: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] - G06F 30/35: Delay-insensitive circuit design, e.g. asynchronous or self-timed - H03K 19/1737: {using multiplexers (H03K19/1738 takes precedence)} - H03K 19/17736: Structural details of routing resources - H03K 19/1776: for memories - G06F 2111/04: Constraint-based CAD - G06F 2111/06: Multi-objective optimisation, e.g. Pareto optimisation using simulated annealing [SA], ant colony algorithms or genetic algorithms [GA] - G06F 2119/10: Noise analysis or noise optimisation - G06F 2119/12: Timing analysis or timing optimisation - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Integrated circuits such as programmable integrated circuits may include programmable logic regions that can be configured to perform custom user functions. The programmable logic regions may produce output signals. The integrated circuit may include interconnects that route selected output signals throughout the integrated circuit. The integrated circuit may include output selection circuitry having output selection and interconnect selection stages. The output selection circuitry may be configured to select which of the output signals produced by the programmable logic regions are provided to the interconnects for routing. The interconnect selection stage may be formed using multiplexing circuits or tristate drivers. Logic design system computing equipment may be used to generate configuration data that can be used to program the output selection circuitry to reduce crosstalk by routing signals away from critical interconnects or by double-driving critical interconnects. ## Claims ### Claim 1 An integrated circuit comprising: at least first and second interconnects; circuitry including a plurality of logic regions that produce output signals; a first selection stage circuitry that receives the output signals and selects at least two output signals from the output signals; a second selection stage circuitry that receives the at least two output signals, wherein the second selection stage circuitry provides a first output signal of the at least two output signals to the first interconnect and provides a second output signal of the at least two output signals to the second interconnect in a first configuration mode, and wherein the second selection stage circuitry provides the second output signal to the first interconnect and provides the first output signal to the second interconnect in a second configuration mode; and an input selection circuit that provides a plurality of input signals to the plurality of logic regions of the circuitry. ### Claim 2 (depends on 1) The integrated circuit defined in claim 1, wherein the second selection stage circuitry comprises: at least first and second multiplexing circuits that receive the at least two output signals from the first selection stage circuitry. ### Claim 3 (depends on 1) The integrated circuit defined in claim 1 wherein the second selection stage circuitry comprises: a first set of tristate drivers that is coupled to the first interconnect, wherein the first set of tristate drivers receives the at least two output signals from the first selection stage circuitry; and a second set of tristate drivers that is coupled to the second interconnect, wherein the second set of tristate drivers receives the at least two output signals from the first selection stage circuitry. ### Claim 4 (depends on 3) The integrated circuit defined in claim 3 further comprising memory elements coupled to the first and the second sets of tristate drivers, wherein the memory elements provides the tristate drivers with static control signals that selectively enable and selectively disable the tristate drivers of the first and second sets of tristate drivers. ### Claim 5 (depends on 4) The integrated circuit defined in claim 4, wherein the second selection stage circuitry enables each of the tristate drivers of the first set of tristate drivers in a third configuration mode. ### Claim 6 (depends on 1) The integrated circuit defined in claim 1 wherein the second selection stage circuitry provides the first output signal to the first interconnect and electrically disconnects the second interconnect in a third configuration mode. ### Claim 7 (depends on 1) The integrated circuit defined in claim 1 wherein the first selection stage circuitry comprises a plurality of multiplexers that receives the output signals and selects the at least two output signals from the output signals. ### Claim 8 (depends on 7) The integrated circuit defined in claim 7 wherein each multiplexer of the plurality of multiplexers receives a subset of the output signals. ### Claim 9 (depends on 1) The integrated circuit defined in claim 1 wherein the first interconnect is formed along a vertical axis of the integrated circuit and wherein the second interconnect is formed along a horizontal axis of the integrated circuit. ### Claim 10 (depends on 1) The integrated circuit defined in claim 1, wherein the integrated circuit comprises first and second metal layers, wherein the first interconnect is formed on the first metal layer, and wherein the second interconnect is formed on the second metal layer. ### Claim 11 (depends on 1) The integrated circuit defined in claim 1, wherein the first interconnect has a first length, and wherein the second interconnect has a second length, wherein the second length is different from the first length. ### Claim 12 (depends on 1) The integrated circuit defined in claim 1, wherein the integrated circuit comprises a programmable integrated circuit and wherein the circuitry comprises a plurality of programmable logic elements that produces the output signals. ### Claim 13 (depends on 1) The integrated circuit defined in claim 1 wherein the first selection stage circuitry comprises a plurality of multiplexers that each receive the output signals from the plurality of logic regions. ### Claim 14 (depends on 1) The integrated circuit defined in claim 1 wherein the integrated circuit includes programmable logic regions arranged in rows and columns, wherein the circuitry including the plurality of logic regions forms a given one of the programmable logic regions, and wherein each logic region of the plurality of logic regions forms a portion of the given programmable logic region. ### Claim 15 An integrated circuit comprising: circuitry that produces a plurality of output signals; driver circuitry; a first multiplexing circuitry that receives the plurality of output signals and selects at least two output signals including first and second output signals from the plurality of output signals, wherein the first multiplexing circuitry comprises a first selection circuit that receives the plurality of output signals and selects the first output signal and a second selection circuit that receives the plurality of output signals and selects the second output signal; and a second multiplexing circuitry that receives the at least two output signals and provides a selected first portion of the at least two output signals to a first portion of the driver circuitry, wherein the second multiplexing circuitry provides a selected second portion of the at least two output signals to a second portion of the driver circuitry. ### Claim 16 (depends on 15) The integrated circuit defined in claim 15 further comprising: a memory element that provides a static output signal to the second multiplexing circuitry for control thereof. ### Claim 17 (depends on 15) The integrated circuit defined in claim 15 further comprising: a first memory element that provides a first static output signal to the second multiplexing circuitry that determines which output signal of the at least two output signals forms the first portion of the at least two output signals; and a second memory element that provides a second static output signal to the second multiplexing circuitry that determines which output signal of the at least two output signals forms the second portion of the at least two output signals. ### Claim 18 (depends on 15) The integrated circuit defined in claim 15 wherein the driver circuitry is coupled to a first and a second interconnect. ### Claim 19 (depends on 18) The integrated circuit defined in claim 18 wherein the first interconnect is formed along a vertical axis of the integrated circuit and wherein the second interconnect is formed along a horizontal axis of the integrated circuit. ### Claim 20 (depends on 15) The integrated circuit defined in claim 15 further comprising: a plurality of interconnects that convey a plurality of signals; and input selection circuitry that is coupled to the plurality of interconnects, wherein the input multiplexer selects input signals from the plurality of signals and provides the selected input signals to the circuitry and wherein the circuitry produces each of the plurality of output signals based on the selected input signals. ### Claim 21 (depends on 15) The integrated circuit defined in claim 15 wherein the integrated circuit includes programmable logic regions arranged in rows and columns and wherein the circuitry forms a given one of the programmable logic regions.