# US 8,541,994 B2 · Switched-mode power supply > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,541,994 B2 - Document ID: US8541994B2 - Status: Granted - Kind: B2 - Application number: 12/966,355 - Filed: 2010-12-13 - Published: 2011-06-23 - Granted: 2013-09-24 - Earliest claimed: 2009-12-18 - Assignees: Realtek Semiconductor Corp. - Applicants: Chen-Chih Huang; Cheng-Pang Chan - Inventors: Chen-Chih Huang; Cheng-Pang Chan - Web page: https://patentgrep.com/patent/US8541994B2 ## CPC - H02M 3/156: with automatic control of output voltage or current, e.g. switching regulators - H02M 3/155: using semiconductor devices only - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) ## Abstract A switched-mode power supply (SMPS) uses an equivalent inductor of bonding wire(s) and lead frame(s) to replace a traditional external inductor. A current-controlled pulse width modulation (PWM) modulator and a current-controlled pulse frequency modulation (PFM) modulator are optionally employed for high frequency switching, so as to mate a low inductance value of the bonding wire(s) and lead frame(s) and achieve reduced cost, low power consumption and low complexity. ## Claims ### Claim 1 A switched-mode power supply (SMPS) for supplying an output current to charge an external capacitor to generate an output voltage, comprising: a first bonding wire; a second bonding wire; and a power conversion chip, comprising: a first pad connected to an end of the first bonding wire; a second pad connected to an end of the second bonding wire; a frequency compensation circuit coupled to the second pad to acquire a feedback voltage, and outputting an error signal according to a reference voltage and the feedback voltage; a current-controlled pulse width modulation (PWM) modulator electrically coupled to the frequency compensation circuit, generating a high-frequency PWM output signal according to the error signal and a high-frequency clock signal; a current-controlled pulse frequency modulation (PFM) modulator electrically coupled to the frequency compensation circuit, generating a high-frequency PFM output signal according to the error signal; a power stage, switching under control to output the output current from a switch node, the switch node connected to the first pad; a selector electrically coupled to the current-controlled PWM modulator, and the current-controlled PFM modulator, activating the current-controlled PWM modulator or the current-controlled PFM modulator according to a selection signal; and a driver electrically coupled to the power stage, the current-controlled PWM modulator and the current-controlled PFM modulator, controlling the switching of the power stage according to the PWM output signal or the PFM output signal; wherein the first bonding wire is electrically coupled to the other end of the second bonding wire, and electrically connected to an end of the external capacitor. ### Claim 2 (depends on 1) The SMPS according to claim 1, wherein the driver is a non-overlap clock generator that generates two non-overlap control signals to the power stage according to the PFM output signal or the PWM output signal respectively. ### Claim 3 (depends on 1) The SMPS according to claim 1 further comprising a high frequency generator that generates the high-frequency clock signal to the current-controlled PWM modulator. ### Claim 4 (depends on 1) The SMPS according to claim 1, wherein a frequency of the PWM output signal or the PFM output signal is higher than 10 MHz. ### Claim 5 (depends on 1) The SMPS according to claim 1, wherein a frequency of the PWM output signal or the PFM output signal is within a range of 100 MHz to 400 MHz. ### Claim 6 (depends on 1) The SMPS according to claim 1, wherein an equivalent inductance value provided by any of the first bonding wire and the second bonding wire is within a range of 1 nH to 10 nH. ### Claim 7 (depends on 1) The SMPS according to claim 1, wherein the current-controlled PWM modulator comprises: an inverter, having an input end receiving the high-frequency clock signal and an output end outputting the PWM output signal; and a voltage-to-current converter electrically coupled to the frequency compensation circuit, converting the error signal into a PWM control current, wherein the PWM control current pulls down the inverter strongly or weakly in response to a magnitude of the error signal, so as to change a duty cycle of the PWM output signal. ### Claim 8 (depends on 7) The SMPS according to claim 7 further comprising a buffer, the buffer being connected to the output end of the inverter and buffering the PWM output signal. ### Claim 9 (depends on 7) The SMPS according to claim 7, wherein the current-controlled PWM modulator further comprises: a first current mirror electrically coupled to the voltage-to-current converter, mirroring the PWM control current to generate a converted current; and a second current mirror, having an input end electrically coupled to an output end of the first current minor and an output end electrically coupled to the inverter, the second current mirror mirroring the converted current to pull down the inverter strongly or weakly. ### Claim 10 (depends on 1) The SMPS according to claim 1, wherein the current-controlled PEW modulator comprises: a voltage-to-current converter electrically coupled to the frequency compensation circuit, converting and generating a PFM control current according to the error signal; a current minor electrically coupled to the voltage-to-current converter, generating a converted current according to the PFM control current; and a current-starved voltage-controlled oscillator (VCO) connected to the current mirror, generating the PFM output signal according to the converted current. ### Claim 11 (depends on 10) The SMPS according to claim 10, further comprising a buffer, the buffer being connected to the current-starved VCO and buffering the PFM output signal. ### Claim 12 (depends on 10) The SMPS according to claim 10, wherein the current-starved VCO comprises a ring oscillator with odd stages. ### Claim 13 (depends on 1) The SNIPS according to claim 1 further comprising a lead frame, Wherein the other ends of the first bonding wire and the second bonding wire are bonded to the lead frame, and connected directly to the external capacitor via a common pin on the lead frame. ### Claim 14 (depends on 1) The SMPS according to claim 1 further comprising a lead frame, wherein the other ends of the first bonding wire and the second bonding wire are bonded to the lead frames, and connected directly to the external capacitor respectively via a first pin and a second pin on the lead frame. ### Claim 15 (depends on 1) The SMPS according to claim 1, wherein the first bonding wire or the second bonding wire is formed of a plurality of bonding wires. ### Claim 16 A switched-mode power supply (SPMS) for supplying an output current to charge an external capacitor to generate an output voltage, and comprising: a first bonding wire; a second bonding wire; and a power conversion chip, comprising: a first pad, connected to an end of the first bonding wire; a second pad, connected to an end of the second bonding wire; a frequency compensation circuit, electrically coupling to the second pad to acquire a feedback voltage, and outputting an error signal according to a reference voltage and the feedback voltage; a current-controlled pulse width modulation (PWM) modulator electrically coupled to the frequency compensation circuit, generating a high-frequency PWM output signal according to a high-frequency clock signal and the error signal; a power stage switching under control to output the output current from a switch node connected to the first pad; and a driver electrically coupled to the power stage and the current-controlled PWM modulator, controlling the switching of the power stage according to the PWM output signal; wherein the first bonding wire is electrically coupled to the other end of the second bonding wire, and electrically connected to an end of the external capacitor. ### Claim 17 (depends on 16) The SMPS according to claim 16, wherein the driver is a non-overlap clock generator that generates two non-overlap control signals to the power stage according to the PWM output signal. ### Claim 18 (depends on 16) The SMPS according to claim 16, further comprising a high frequency generator that generates a high-frequency clock signal to the current-controlled PWM modulator. ### Claim 19 (depends on 16) The SMPS according to claim 16, wherein a frequency of the PWM output signal is higher than 10 MHz. ### Claim 20 (depends on 16) The SMPS according to claim 16, where frequency of the PWM output signal is within a range of 100 MHz to 400 MHz. ### Claim 21 (depends on 16) The SMPS according to claim 16, wherein an equivalent inductance value is provided by any of the first bonding wire and the second bonding wire is within a range of 1 nH to 10 nH. ### Claim 22 (depends on 16) The SMPS according to claim 16, wherein the current-controlled PWM modulator comprises: an inverter, having an input end receiving the high-frequency clock signal, and an output end outputting the PWM output signal; and a voltage-to-current converter electrically coupled to the frequency compensation circuit, for converting the error signal into a PWM control current, wherein the PWM control current pulls down the inverter strongly or weakly in response to a magnitude of the error signal, so as to change a duty cycle of the PWM output signal. ### Claim 23 (depends on 22) The SMPS according to claim 22 further comprising a buffer, the buffer being connected to the output end of the inverter and buffering the PWM output signal. ### Claim 24 (depends on 22) The SMPS according to claim 22, further comprising: a first current mirror electrically coupled to the voltage-to-current converter, mirroring the PWM control current to generate a converted current; and a second current mirror, having an input end electrically coupled to an output end of the first current mirror, and an output end electrically coupled to the inverter, the second current mirror mirroring the converted current to pull down the inverter strongly or weakly. ### Claim 25 (depends on 16) The SMPS according to claim 16, further comprising a lead frame, wherein the other ends of the first bonding wire and the second bonding wire are bonded to the lead frame, and connected directly to the external capacitor via a common pin on the lead frame. ### Claim 26 (depends on 16) The SMPS according to claim 16 further comprising a lead frame, wherein the other ends of the first bonding wire and the second bonding wire are bonded to the lead frames, and connected directly to the external capacitor respectively via a first pin and a second pin on the lead frame. ### Claim 27 (depends on 16) The SMPS according to claim 16, wherein the first bonding wire or the second bonding wire is formed of a plurality of bonding wires. ### Claim 28 A switched-mode power supply (SMPS) for supplying an output current to charge an external capacitor to generate an output voltage, and comprising: a first bonding wire; a second bonding wire; and a power conversion chip, comprising: a first pad, connected to an end of the first bonding wire; a second pad, connected to an end of the second bonding wire; a frequency compensation circuit, electrically coupling to the second pad to acquires a feedback voltage, and outputting an error signal according to a reference voltage and the feedback voltage; a current-controlled pulse frequency modulation (PFM) modulator electrically coupled to the frequency compensation circuit, generating a high-frequency PFM output signal according to the error signal; a power stage, switching under control to output the output current from a switch node connected to the first pad; and a driver electrically coupled to the power stage and the current-controlled PFM modulator, controlling the switching of the power stage according to the PFM output signal; wherein the first bonding wire is electrically coupled to the other end of the second bonding wire, and electrically connected to an end of the external capacitor. ### Claim 29 (depends on 28) The SMPS according to claim 28, wherein the driver is a non-overlap clock generator that generates two non-overlap control signals to the power stage according to the PFM output signal. ### Claim 30 (depends on 28) The SMPS according to claim 28, wherein an equivalent inductance value provided by any of the first bonding wire and the second bonding wire is within a range of 1 nH to 10 nH. ### Claim 31 (depends on 28) The SMPS according to claim 28, wherein a frequency of the PFM output signal is higher than 10 MHz. ### Claim 32 (depends on 28) The SNIPS according to claim 28, wherein a frequency of the PFM output signal is within a range of 100 MHz to 400 MHz. ### Claim 33 (depends on 28) The SMPS according to claim 28, wherein the current-controlled PFM modulator comprises: a voltage-to-current converter electrically coupled to the frequency compensation circuit, converting and generating a PFM control current according to the error signal; a current-starved voltage-controlled oscillator (VCO), generating the PFM output signal according to the PFM control current; and a buffer connected to the current-starved VCO, buffering the PFM output signal from the current-starved VCO. ### Claim 34 (depends on 33) The SMPS according to claim 33 further comprising a current mirror, the current mirror electrically coupling to the voltage-to-current converter and mirroring the PFM control current to generate a converted current to the current-starved VCO. ### Claim 35 (depends on 33) The SMPS according to claim 33, wherein the current-starved VCO comprises a ring oscillator with odd stages. ### Claim 36 (depends on 28) The SMPS according to claim 28, further comprising a lead frame, wherein the other ends of the first bonding wire and the second bonding wire are bonded to the lead frame, and connected directly to the external capacitor via a common pin on the lead frame. ### Claim 37 (depends on 28) The SMPS according to claim 28, further comprising a lead frame, wherein the other ends of the first bonding wire and the second bonding wire are bonded to the lead frame, and connected directly to the external capacitor respectively via a first pin and a second pin on the lead frame. ### Claim 38 (depends on 28) The SMPS according to claim 28, wherein the first bonding wire or the second bonding wire is formed of a plurality of bonding wires.