# US 8,541,893 B2 · Semiconductor memory device and power line arrangement method thereof

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- Number: US 8,541,893 B2
- Document ID: US8541893B2
- Status: Granted
- Kind: B2
- Application number: 11/229,257
- Filed: 2005-09-16
- Published: 2006-03-23
- Granted: 2013-09-24
- Earliest claimed: 2004-09-20
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Sung-Hoon Kim; Young-Chul Cho; Kwang-Il Park; Seong-Jin Jang
- Inventors: Sung-Hoon Kim; Young-Chul Cho; Kwang-Il Park; Seong-Jin Jang
- Web page: https://patentgrep.com/patent/US8541893B2

## CPC

- H10W 20/427: {Power or ground buses}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor memory device and a power line arrangement method are disclosed. The semiconductor memory device includes a plurality of pads, each pad including an upper pad and a lower pad arranged below the upper pad, wherein pad power lines are arranged below the lower pads of the plurality of pads in a direction of crossing the pads to interconnect the pads that transmit the same level of electrical power among the plurality of pads.

## Claims

### Claim 1

A semiconductor memory device, comprising:
a plurality of pads, each pad including an upper pad layer and a lower pad layer arranged below the upper pad layer, the plurality of pads including:
(i) a first set of pads to be supplied with a first level of electrical power, and
(ii) a second set of pads to be supplied with a second level of electrical power;
a first pad power line arranged below the lower pad layers of the plurality of pads, the first pad power line extending in a direction crossing the plurality of pads so as to connect the first set of pads to each other; and
a second pad power line arranged below the lower pad layers of the plurality of pads, the second pad power line extending in the direction crossing the plurality of pads so as to connect the second set of pads to each other.

### Claim 2 (depends on 1)

The device of claim 1, wherein the upper and lower pad layers and the first and second pad power lines are made of a metal.

### Claim 3 (depends on 1)

The device of claim 1, wherein the upper and lower pad layers are made of a metal, and
the first and second pad power lines are made of tungsten.

### Claim 4 (depends on 1)

The device of claim 1, wherein the upper and lower pad layers of each of the plurality of pads are electrically connected, and
the lower pad layers of the first set of pads and the first pad power line are electrically interconnected, and
the lower pad layers of the second set of pads and the second pad power line are electrically interconnected.

### Claim 5 (depends on 1)

The device of claim 1, wherein the first and second pad power lines transmit at least one of a power voltage power and a ground voltage power.

### Claim 6 (depends on 1)

The device of claim 1, wherein the first and second pad power lines transmit at least one of a power voltage power, a ground voltage power, a substrate voltage power, a high voltage power, and a reference voltage power.

### Claim 7 (depends on 1)

The device of claim 1, further comprising:
a first sub pad power line arranged in a perpendicular direction to the first pad power line; and
a second sub pad power line arranged in a perpendicular direction to the second pad power line.

### Claim 8 (depends on 7)

The device of claim 7, wherein the first pad power line and the first sub pad power line transmit the same level of electrical power and are arranged in the same layer, and
the second pad power line and the second sub pad power line transmit the same level of electrical power and are arranged in the same layer.

### Claim 9 (depends on 8)

The device of claim 8, wherein the upper and lower pad layers are made of a metal, and
the first and second pad power lines and the first and second sub pad power lines are made of tungsten.

### Claim 10 (depends on 8)

The device of claim 8, wherein the upper and lower pad layers, the first and second pad power lines, and the first and second sub pad power lines are made of a metal.

### Claim 11 (depends on 7)

The device of claim 7, wherein the first pad power line and the first sub pad power line transmit a different level of electrical power than the second pad power line and the second sub pad power line, and
the first and second sub pad power lines are arranged below a layer in which the first and second pad power lines are arranged.

### Claim 12 (depends on 11)

The device of claim 11, wherein the upper and lower pad layers and the first and second pad power lines are made of a metal, and
the first and second sub pad power lines are made of tungsten.

### Claim 13 (depends on 11)

The device of claim 11, wherein the upper and lower pad layers, the first and second pad power lines, and the first and second sub pad power lines are made of a metal.

### Claim 14 (depends on 7)

The device of claim 7, wherein the upper and lower pad layers of each of the plurality of pads are electrically connected,
the lower pad layers of the first set of pads, the first power line, and the first sub pad power line are electrically interconnected, and
the lower pad layers of the second set of pads, the second power line, and the second sub power line are electrically interconnected.

### Claim 15 (depends on 7)

The device of claim 7, wherein the first and second pad power lines transmit at least one of a power voltage power and a ground voltage power.

### Claim 16 (depends on 7)

The device of claim 7, wherein the first and second pad power lines transmit at least one of a power voltage power, a ground voltage power, a substrate voltage power, a high voltage power, and a reference voltage power.

### Claim 17 (depends on 1)

The device of claim 1, further comprising:
a memory cell array;
a peripheral circuit for controlling data input/output to/from the memory cell array; and
array and peripheral circuit power lines for supplying the electrical power to the memory cell array and the peripheral circuit arranged above the memory cell array and the peripheral circuit;
wherein the electrical power is applied from the outside of the device, and
the upper and the lower pad layers of each of the plurality of pads are arranged in two layers which are the same layers as the array and peripheral circuit power lines.

### Claim 18 (depends on 17)

The device of claim 17, wherein the array and peripheral circuit power lines are arranged in three layers in a perpendicular direction to each other,
the first and second pad power lines are arranged in a first layer,
the lower pad layers are arranged in a second layer, and
the upper pad layers are arranged in a third layer.

### Claim 19 (depends on 18)

The device of claim 18, further comprising:
a first sub pad power line arranged in a perpendicular direction to the first pad power line; and
a second sub pad power line arranged in a perpendicular direction to the second pad power line,
wherein the first and second sub pad power lines are arranged in a dummy portion formed below the lower pad layers for matching a step height with the memory cell array and the peripheral circuit.

### Claim 20 (depends on 19)

The device of claim 19, wherein the upper and lower pad layers and the first and second pad power lines are made of a metal, and
the first and second sub pad power lines are made of tungsten.

### Claim 21 (depends on 18)

The device of claim 18, wherein the peripheral circuit includes a predetermined number of internal voltage generators which generate different level of voltages, and
a predetermined number of power lines for supplying the respective internal voltage generators with the electrical power from the upper pad layers of the plurality of pads are arranged on the same layer as the upper pad layers.

### Claim 22 (depends on 21)

The device of claim 21, wherein a predetermined number of the power lines for supplying the respective internal voltage generators with the electrical power from the lower pad layers of the plurality of pads are arranged on the same layer as the lower pad layers.

### Claim 23 (depends on 17)

The device of claim 17, wherein the array and peripheral circuit power lines are arranged in two layers, and
the first and second pad power lines are arranged in a dummy portion formed below the lower pad layers to match a step height with a region where the memory cell array and the peripheral circuit.

### Claim 24 (depends on 23)

The device of claim 23, wherein the upper and lower pad layers are made of a metal, and
the first and second pad power lines are made of tungsten.

### Claim 25 (depends on 17)

The device of claim 17, wherein first and second sub pad power lines are additionally arranged in a perpendicular direction to the first and second pad power lines,
the first and second pad power lines and the upper and lower pad layers are separately arranged in different three layers,
some of the first and second sub pad power lines are arranged in the same layer as the first and second pad power lines, and
the rest of the first and second sub power lines are arranged in a different layer from the first and second pad power lines and the upper and lower pad layers.

### Claim 26 (depends on 25)

The device of claim 25, wherein the first and second pad power lines, the upper and lower pad layers, and the first and second sub pad power lines are made of a metal.

### Claim 27 (depends on 17)

The device of claim 17, wherein the array and peripheral circuit power lines are arranged in at least two layers to overlap, and
the power lines arranged to overlap transmit different level of electrical powers.

### Claim 28 (depends on 27)

The device of claim 27, wherein one of the power lines arranged to overlap and one of the power lines arranged to overlap adjacent to the power lines arranged to overlap are lines transmitting the same level of electrical power, and one of the power lines which transmit the same level of electrical power and are arranged to overlap and one of the adjacent power lines arranged to overlap are arranged in different layers.

### Claim 29 (depends on 17)

The device of claim 17, wherein the array and peripheral circuit power lines are arranged in at least three layers including the at least two layers,
the array and peripheral circuit power lines arranged in the at least two layers among the at least three layers are arranged to overlap, and
the power lines arranged to overlap are lines which transmit different levels of electrical power.

### Claim 30 (depends on 29)

The device of claim 29, wherein one of the power lines arranged to overlap and one of the power lines arranged to overlap adjacent to the power lines arranged to overlap are lines transmitting the same level of electrical power, and one of the power lines which transmits the same level of electrical power and are arranged to overlap and one of the adjacent power lines arranged to overlap are arranged in different layers.

### Claim 31 (depends on 29)

The device of claim 29, wherein the upper and lower pad layers of each of the plurality of pads are arranged in two layers which are the same layers as the array and peripheral circuit power lines, and
the first and second pad power lines crossing the pads are arranged below the lower pad layers of the plurality of pads to connect the pads which transmit the same level of electrical power among the plurality of pads.

### Claim 32 (depends on 31)

The device of claim 31, wherein the array and peripheral circuit power lines are arranged in three layers in a perpendicular direction to each other,
the first and second pad power lines are arranged in a first layer,
the lower pad layers are arranged in a second layer, and
the upper pad layers are arranged in a third layer.

### Claim 33 (depends on 32)

The device of claim 32, further comprising:
a first sub pad power line arranged in a perpendicular direction to the first pad power line; and
a second sub pad power line arranged in a perpendicular direction to the second pad power line,
wherein the first and second sub pad power lines are arranged in a dummy portion formed below the lower pad layers for matching a step height with the memory cell array and the peripheral circuit.

### Claim 34 (depends on 31)

The device of claim 31, wherein the peripheral circuit includes a predetermined number of internal voltage generators which generate different levels of voltages, and
a predetermined number of power lines for supplying the respective internal voltage generators with the electrical power from the upper pad layers of the plurality of pads arranged in the same layer as the upper pad layers.

### Claim 35 (depends on 34)

The device of claim 34, wherein a predetermined number of the power lines for supplying the respective internal voltage generators with the electrical power from the lower pad layers of the plurality of pads are arranged in the same layer as the lower pad layers.