# US 8,541,890 B2 · Substrate based unmolded package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,541,890 B2 - Document ID: US8541890B2 - Status: Granted - Kind: B2 - Application number: 11/180,367 - Filed: 2005-07-12 - Published: 2006-01-12 - Granted: 2013-09-24 - Earliest claimed: 2002-08-30 - Assignees: Fairchild Semiconductor Corporation - Applicants: Rajeev Joshi - Inventors: Rajeev Joshi - Web page: https://patentgrep.com/patent/US8541890B2 ## CPC - H10W 70/479: {on or in insulating or insulated package substrates, interposers, or redistribution layers} - H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00} - H10W 72/0198: {batch processes} - H10W 72/50: Bond wires - H10W 72/884: {Die-attach connectors and bond wires} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a lead frame structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead. ## Claims ### Claim 1 A semiconductor die package comprising: a substrate comprising a lead frame structure having a plurality of leads having lead surfaces at least two die attach regions electrically isolated from each other, and a molding material contacting the lead frame structure, wherein an exterior surface of the molding material is substantially coplanar with the lead surfaces and wherein a major surface of the substrate the at least two die attach regions and the including the exterior surface and the lead surfaces is substantially flat and extends from one edge of the substrate to an opposite edge of the substrate, wherein the lead surfaces are free of the molding material; and a semiconductor die attached to at least two die attach regions of the major surface of the substrate. ### Claim 2 (depends on 1) The semiconductor die package of claim 1 wherein the semiconductor die comprises a vertical transistor. ### Claim 3 (depends on 1) The semiconductor die package of claim 1 wherein the semiconductor die comprises a power MOSFET. ### Claim 4 (depends on 1) The semiconductor die package of claim 1 wherein the semiconductor die package is a purely electrical device. ### Claim 5 (depends on 4) The semiconductor die package of claim 4 wherein the semiconductor die is free of an optical emitter and an optical receiver. ### Claim 6 (depends on 5) The method of claim 5 further comprising: depositing an encapsulating material on the semiconductor die to form a semiconductor die package, wherein the semiconductor die package is a purely electrical device. ### Claim 7 (depends on 6) The method of claim 6 wherein the encapsulating material is different than the molding material. ### Claim 8 (depends on 1) The semiconductor die package of claim 1 wherein the substrate consists of the molding material and the lead frame structure. ### Claim 9 (depends on 1) The semiconductor die package of claim 1 wherein the molding material has a thickness substantially equal to a thickness of the lead frame structure. ### Claim 10 (depends on 1) The semiconductor die package of claim 1 wherein the lead frame structure comprises a plated structure. ### Claim 11 (depends on 1) The semiconductor die package of claim 1 wherein the lead frame structure further comprises a die attach region and wherein the leads extend away from the die attach region. ### Claim 12 (depends on 1) The semiconductor die package of claim 1 wherein the lead frame structure comprises grooves and wherein the molding material fills the grooves. ### Claim 13 (depends on 1) The semiconductor die package of claim 1 further comprising conductive structures on the lead surfaces. ### Claim 14 (depends on 13) The semiconductor die package of claim 13 wherein the conductive structures are solder structures. ### Claim 15 (depends on 1) The semiconductor die package of claim 1 further comprising conductive structures comprising solder on the lead surfaces in the major surface. ### Claim 16 (depends on 1) The semiconductor die package of claim 1 wherein the die is a vertical mosfet with gate and source regions on one surface, wherein the gate region is attached to one die attach region and the source region is attached to another die attach region. ### Claim 17 A semiconductor die package comprising: a substrate comprising a lead frame structure having a plurality of leads having lead surfaces, and a molding material contacting the lead frame structure, wherein an exterior surface of the molding material is substantially coplanar with the lead surfaces and forms at least part of a flat major surface of the substrate; wherein the flat major surface has at least two die attach regions electrically isolated from each other; a semiconductor die attached to at least two die attach regions of the flat major surface of the substrate; and an encapsulating material covering the semiconductor die, wherein the encapsulating material is different than the molding material, and wherein the lead surfaces are free of the molding material. ### Claim 18 (depends on 17) The semiconductor die package of claim 17 wherein the encapsulating material completely covers and is in contact with the semiconductor die. ### Claim 19 (depends on 17) The semiconductor die package of claim 17 wherein the semiconductor die comprises a vertical transistor. ### Claim 20 (depends on 17) The semiconductor die package of claim 17 further comprising a wire coupling the semiconductor die to the substrate. ### Claim 21 (depends on 17) The semiconductor die package of claim 17 wherein the semiconductor die comprises a power MOSFET. ### Claim 22 (depends on 17) The semiconductor die package of claim 17 wherein the molding material has a thickness substantially equal to a thickness of the lead frame structure. ### Claim 23 (depends on 17) The semiconductor die package of claim 17 wherein the lead frame structure has a first surface which forms a die attach surface, and a second surface, opposite the first surface. ### Claim 24 (depends on 17) The semiconductor die package of claim 17 wherein the lead frame structure has a first surface which forms a die attach surface, and a second surface, opposite the first surface, and wherein the first surface has an area greater than the second surface. ### Claim 25 (depends on 17) The semiconductor die package of claim 17 wherein the lead frame structure comprises copper. ### Claim 26 (depends on 17) The semiconductor die package of claim 17 wherein the lead frame structure has a first surface which forms a die attach surface, and a second surface, opposite the first surface, and wherein the molding material covers the second surface. ### Claim 27 (depends on 17) The semiconductor die package of claim 17 wherein the die is a vertical mosfet with gate and source regions on one surface, wherein the gate region is attached to one die attach region and the source region is attached to another die attach region. ### Claim 28 A method comprising: forming a substrate comprising a lead frame structure having a plurality of leads having lead surfaces and at least two die attach regions, electrically isolated from each other, and a molding material contacting the lead frame structure, wherein an exterior surface of the molding material is substantially coplanar with the lead surfaces and forms at least part of a flat major surface of the substrate; and attaching a semiconductor die to the at least two die attach regions of the major surface of the substrate. ### Claim 29 (depends on 28) The method of claim 28 wherein the molding material has a thickness substantially equal to a thickness of the lead frame structure. ### Claim 30 (depends on 28) The method of claim 28 wherein the lead frame structure has a first surface which forms a die attach surface, and a second surface, opposite the first surface, and wherein the first surface has an area greater than the second surface. ### Claim 31 (depends on 28) The method of claim 28 further comprising depositing conductive structures on the lead surfaces. ### Claim 32 (depends on 31) The method of claim 31 wherein the conductive structures are solder structures. ### Claim 33 (depends on 28) The method of claim 28 further comprising depositing conductive structures on the major surface. ### Claim 34 (depends on 33) The method of claim 33 wherein the conductive structures are solder structures. ### Claim 35 (depends on 28) The semiconductor die package of claim 28 wherein the die is a vertical mosfet with gate and source regions on one surface, wherein the gate region is attached to one die attach region and the source region is attached to another die attach region.