# US 8,541,887 B2 · Layered chip package and method of manufacturing same

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- Number: US 8,541,887 B2
- Document ID: US8541887B2
- Status: Granted
- Kind: B2
- Application number: 12/875,710
- Filed: 2010-09-03
- Published: 2012-03-08
- Granted: 2013-09-24
- Earliest claimed: 2010-09-03
- Assignees: Headway Technologies, Inc.; SAE Magnetics (H.K.) Ltd.
- Applicants: Yoshitaka Sasaki; Hiroyuki Ito; Hiroshi Ikejima; Atsushi Iijima
- Inventors: Yoshitaka Sasaki; Hiroyuki Ito; Hiroshi Ikejima; Atsushi Iijima
- Web page: https://patentgrep.com/patent/US8541887B2

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/0198: {batch processes}
- H10W 90/00: Package configurations
- H10P 72/7416: {used during dicing or grinding}
- H10W 46/103: {alphanumeric information, e.g. words, letters or serial numbers}
- H10W 46/401: {for identification or tracking}
- H10W 46/501: {for use before dicing}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/652: Cross-sectional shapes
- H10W 70/654: Top-view layouts
- H10W 70/655: Fan-out layouts
- H10W 70/66: Conductive materials thereof
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01335: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/072: {of bump connectors}
- H10W 72/07223: {Active alignment, e.g. using optical alignment using marks or sensors}
- H10W 72/07232: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/07323: {Active alignment, e.g. using optical alignment using marks or sensors}
- H10W 72/07332: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07336: {Soldering or alloying}
- H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/354: {comprising polymers}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/834: {Interconnections on sidewalls of chips}
- H10W 72/9223: {with redistribution layers [RDL]}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/147: {the encapsulations being multilayered}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/271: {the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement}
- H10W 90/722: {between stacked chips}
- H10W 90/732: {between stacked chips}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including first and second layer portions; and a plurality of first and second terminals that are disposed on the top and bottom surfaces of the main part, respectively, and are electrically connected to the plurality of wires. Each layer portion includes a semiconductor chip having a first surface and a second surface opposite thereto, and includes a plurality of electrodes. The electrodes are disposed on a side of the semiconductor chip opposite to the second surface. The first and second layer portions are bonded to each other such that the respective second surfaces face each other. The first terminals are formed by using the electrodes of the first layer portion, and the second terminals are formed by using the electrodes of the second layer portion.

## Claims

### Claim 1

A layered chip package comprising:
a main body having a top surface, a bottom surface, and four side surfaces; and
wiring that includes a plurality of wires disposed on at least one of the side surfaces of the main body, wherein:
the main body includes: a main part that includes a first layer portion and a second layer portion stacked, the main part having a top surface and a bottom surface; a plurality of first terminals that are disposed on the top surface of the main part and electrically connected to the plurality of wires; and a plurality of second terminals that are disposed on the bottom surface of the main part and electrically connected to the plurality of wires;
each of the first and second layer portions includes a semiconductor chip and a plurality of electrodes, the semiconductor chip having a first surface and a second surface opposite to the first surface;
the plurality of electrodes are disposed on a side of the semiconductor chip opposite to the second surface;
the first layer portion and the second layer portion are bonded to each other such that the respective second surfaces face each other;
the plurality of first terminals are formed by using the plurality of electrodes of the first layer portion;
the plurality of second terminals are formed by using the plurality of electrodes of the second layer portion;
the plurality of electrodes of the first layer portion include one or more electrodes that are not used to form the plurality of first terminals; and
the plurality of electrodes of the second layer portion include one or more electrodes that are not used to form the plurality of second terminals.

### Claim 2 (depends on 1)

The layered chip package according to claim 1, wherein:
the plurality of electrodes of the first layer portion and those of the second layer portion have the same layout; and
the plurality of electrodes include a plurality of first terminal component parts that are used to form the plurality of first terminals in the first layer portion, and a plurality of second terminal component parts that are used to form the plurality of second terminals in the second layer portion.

### Claim 3 (depends on 2)

The layered chip package according to claim 2, wherein the plurality of electrodes further include one or more connecting parts that electrically connect one of the first terminal component parts and one of the second terminal component parts to each other.

### Claim 4 (depends on 1)

The layered chip package according to claim 1, wherein:
the plurality of electrodes include a plurality of chip connection electrodes for electrical connection to the semiconductor chip; and
in at least one of the first and second layer portions, the plurality of chip connection electrodes are in contact with and electrically connected to the semiconductor chip.

### Claim 5 (depends on 1)

The layered chip package according to claim 1, wherein the semiconductor chip includes a plurality of memory cells.

### Claim 6 (depends on 1)

The layered chip package according to claim 1, wherein:
the semiconductor chip has four side surfaces;
each of the first and second layer portions further includes an insulating portion that covers at least one of the four side surfaces of the semiconductor chip; and
the insulating portion has at least one end face that is located in the at least one of the side surfaces of the main body on which the plurality of wires are disposed.

### Claim 7

A composite layered chip package comprising a plurality of subpackages stacked, every vertically adjacent two of the subpackages being electrically connected to each other, wherein:
each of the plurality of subpackages includes: a main body having a top surface, a bottom surface and four side surfaces; and wiring that includes a plurality of wires disposed on at least one of the side surfaces of the main body;
the main body includes: a main part that includes a first layer portion and a second layer portion stacked, the main part having a top surface and a bottom surface; a plurality of first terminals that are disposed on the top surface of the main part and electrically connected to the plurality of wires; and a plurality of second terminals that are disposed on the bottom surface of the main part and electrically connected to the plurality of wires;
each of the first and second layer portions includes a semiconductor chip and a plurality of electrodes, the semiconductor chip having a first surface and a second surface opposite to the first surface;
the plurality of electrodes are disposed on a side of the semiconductor chip opposite to the second surface;
the first layer portion and the second layer portion are bonded to each other such that the respective second surfaces face each other;
the plurality of first terminals are formed by using the plurality of electrodes of the first layer portion;
the plurality of second terminals are formed by using the plurality of electrodes of the second layer portion;
the plurality of electrodes of the first layer portion include one or more electrodes that are not used to form the plurality of first terminals;
the plurality of electrodes of the second layer portion include one or more electrodes that are not used to form the plurality of second terminals; and
for any vertically adjacent two of the subpackages, the plurality of second terminals of the upper one of the subpackages are electrically connected to the plurality of first terminals of the lower one.

### Claim 8 (depends on 7)

The composite layered chip package according to claim 7, wherein:
the plurality of electrodes of the first layer portion and those of the second layer portion have the same layout; and
the plurality of electrodes include a plurality of first terminal component parts that are used to form the plurality of first terminals in the first layer portion, and a plurality of second terminal component parts that are used to form the plurality of second terminals in the second layer portion.

### Claim 9 (depends on 8)

The composite layered chip package according to claim 8, wherein the plurality of electrodes further include one or more connecting parts that electrically connect one of the first terminal component parts and one of the second terminal component parts to each other.

### Claim 10 (depends on 7)

The composite layered chip package according to claim 7, wherein:
the plurality of electrodes include a plurality of chip connection electrodes for electrical connection to the semiconductor chip; and
in at least one of the first and second layer portions, the plurality of chip connection electrodes are in contact with and electrically connected to the semiconductor chip.

### Claim 11 (depends on 7)

The composite layered chip package according to claim 7, wherein the semiconductor chip includes a plurality of memory cells.

### Claim 12

A layered chip package comprising:
a main body having a top surface, a bottom surface, and four side surfaces; and
wiring that includes a plurality of wires disposed on at least one of the side surfaces of the main body, wherein:
the main body includes: a main part that includes a first layer portion and a second layer portion stacked, the main part having a top surface and a bottom surface; a plurality of first terminals that are disposed on the top surface of the main part and electrically connected to the plurality of wires; and a plurality of second terminals that are disposed on the bottom surface of the main part and electrically connected to the plurality of wires;
each of the first and second layer portions includes a semiconductor chip and a plurality of electrodes, the semiconductor chip having a first surface and a second surface opposite to the first surface;
the plurality of electrodes are disposed on a side of the semiconductor chip opposite to the second surface;
the first layer portion and the second layer portion are bonded to each other such that the respective second surfaces face each other;
the plurality of first terminals are formed by using the plurality of electrodes of the first layer portion;
the plurality of second terminals are formed by using the plurality of electrodes of the second layer portion;
the plurality of second terminals are positioned to overlap the plurality of first terminals as viewed in a direction perpendicular to the top surface of the main body;
the plurality of second terminals are electrically connected to corresponding ones of the first terminals via the respective wires to constitute a plurality of pairs of the first and second terminals, the first and second terminals in each of the pairs being electrically connected to each other; and
the plurality of pairs include a plurality of non-overlapping terminal pairs, each of the non-overlapping terminal pairs consisting of any one of the first terminals and any one of the second terminals, the first and second terminals in each of the non-overlapping terminal pairs being electrically connected to each other and being positioned not to overlap each other as viewed in the direction perpendicular to the top surface of the main body.

### Claim 13 (depends on 12)

The layered chip package according to claim 12, wherein the plurality of pairs further include a plurality of overlapping terminal pairs, each of the overlapping terminal pairs consisting of any one of the first terminals and any one of the second terminals, the first and second terminals in each of the overlapping terminal pairs being electrically connected to each other and being positioned to overlap each other as viewed in the direction perpendicular to the top surface of the main body.

### Claim 14 (depends on 12)

The layered chip package according to claim 12, wherein the plurality of wires include: a chip connection wire that is electrically connected to any one of the plurality of non-overlapping terminal pairs and used for electrical connection to the semiconductor chip of at least one of the first and second layer portions; and a bypass wire that is electrically connected to any one of the plurality of non-overlapping terminal pairs and to neither of the semiconductor chips included in the first and second layer portions.

### Claim 15

A layered chip package comprising:
a main body having a top surface, a bottom surface, and four side surfaces; and
wiring that includes a plurality of wires disposed on at least one of the side surfaces of the main body, wherein:
the main body includes: a main part that includes a first layer portion and a second layer portion stacked, the main part having a top surface and a bottom surface; a plurality of first terminals that are disposed on the top surface of the main part and electrically connected to the plurality of wires; and a plurality of second terminals that are disposed on the bottom surface of the main part and electrically connected to the plurality of wires;
each of the first and second layer portions includes a semiconductor chip and a plurality of electrodes, the semiconductor chip having a first surface and a second surface opposite to the first surface;
the plurality of electrodes are disposed on a side of the semiconductor chip opposite to the second surface;
the first layer portion and the second layer portion are bonded to each other such that the respective second surfaces face each other;
the plurality of first terminals are formed by using the plurality of electrodes of the first layer portion;
the plurality of second terminals are formed by using the plurality of electrodes of the second layer portion;
one of the first and second layer portions is a first-type layer portion, whereas the other of the first and second layer portions is a second-type layer portion;
in the first-type layer portion, the semiconductor chip is electrically connected to two or more of the plurality of wires; and
in the second-type layer portion, the semiconductor chip is electrically connected to none of the wires.

### Claim 16 (depends on 15)

The layered chip package according to claim 15, wherein the semiconductor chip of the first-type layer portion is a normally functioning one, whereas the semiconductor chip of the second-type layer portion is a malfunctioning one.

### Claim 17

A composite layered chip package comprising a plurality of subpackages stacked, every vertically adjacent two of the subpackages being electrically connected to each other, wherein:
each of the plurality of subpackages includes: a main body having a top surface, a bottom surface and four side surfaces; and wiring that includes a plurality of wires disposed on at least one of the side surfaces of the main body;
the main body includes: a main part that includes a first layer portion and a second layer portion stacked, the main part having a top surface and a bottom surface;
a plurality of first terminals that are disposed on the top surface of the main part and electrically connected to the plurality of wires; and a plurality of second terminals that are disposed on the bottom surface of the main part and electrically connected to the plurality of wires;
each of the first and second layer portions includes a semiconductor chip and a plurality of electrodes, the semiconductor chip having a first surface and a second surface opposite to the first surface;
the plurality of electrodes are disposed on a side of the semiconductor chip opposite to the second surface;
the first layer portion and the second layer portion are bonded to each other such that the respective second surfaces face each other;
the plurality of first terminals are formed by using the plurality of electrodes of the first layer portion;
the plurality of second terminals are formed by using the plurality of electrodes of the second layer portion;
the plurality of second terminals are positioned to overlap the plurality of first terminals as viewed in a direction perpendicular to the top surface of the main body;
the plurality of second terminals are electrically connected to corresponding ones of the first terminals via the respective wires to constitute a plurality of pairs of the first and second terminals, the first and second terminals in each of the pairs being electrically connected to each other;
the plurality of pairs include a plurality of non-overlapping terminal pairs, each of the non-overlapping terminal pairs consisting of any one of the first terminals and any one of the second terminals, the first and second terminals in each of the non-overlapping terminal pairs being electrically connected to each other and being positioned not to overlap each other as viewed in the direction perpendicular to the top surface of the main body; and
for any vertically adjacent two of the subpackages, the plurality of second terminals of the upper one of the subpackages are electrically connected to the plurality of first terminals of the lower one.

### Claim 18 (depends on 17)

The composite layered chip package according to claim 17, wherein the plurality of pairs further include a plurality of overlapping terminal pairs, each of the overlapping terminal pairs consisting of any one of the first terminals and any one of the second terminals, the first and second terminals in each of the overlapping terminal pairs being electrically connected to each other and being positioned to overlap each other as viewed in the direction perpendicular to the top surface of the main body.

### Claim 19 (depends on 17)

The composite layered chip package according to claim 17, wherein the plurality of wires include: a chip connection wire that is electrically connected to any one of the plurality of non-overlapping terminal pairs and used for electrical connection to the semiconductor chip of at least one of the first and second layer portions; and a bypass wire that is electrically connected to any one of the plurality of non-overlapping terminal pairs and to neither of the semiconductor chips included in the first and second layer portions.

### Claim 20

A composite layered chip package comprising a plurality of subpackages stacked, every vertically adjacent two of the subpackages being electrically connected to each other, wherein:
each of the plurality of subpackages includes: a main body having a top surface, a bottom surface and four side surfaces; and wiring that includes a plurality of wires disposed on at least one of the side surfaces of the main body;
the main body includes: a main part that includes a first layer portion and a second layer portion stacked, the main part having a top surface and a bottom surface; a plurality of first terminals that are disposed on the top surface of the main part and electrically connected to the plurality of wires; and a plurality of second terminals that are disposed on the bottom surface of the main part and electrically connected to the plurality of wires;
each of the first and second layer portions includes a semiconductor chip and a plurality of electrodes, the semiconductor chip having a first surface and a second surface opposite to the first surface;
the plurality of electrodes are disposed on a side of the semiconductor chip opposite to the second surface;
the first layer portion and the second layer portion are bonded to each other such that the respective second surfaces face each other;
the plurality of first terminals are formed by using the plurality of electrodes of the first layer portion;
the plurality of second terminals are formed by using the plurality of electrodes of the second layer portion;
for any vertically adjacent two of the subpackages, the plurality of second terminals of the upper one of the subpackages are electrically connected to the plurality of first terminals of the lower one;
in at least one of the plurality of subpackages, one of the first and second layer portions is a first-type layer portion, whereas the other of the first and second layer portions is a second-type layer portion;
in the first-type layer portion, the semiconductor chip is electrically connected to two or more of the plurality of wires; and
in the second-type layer portion, the semiconductor chip is electrically connected to none of the wires,
the composite layered chip package further comprising an additional portion that is electrically connected to any of the plurality of subpackages, the additional portion including:
at least one additional semiconductor chip; and
additional portion wiring that defines electrical connections between the at least one additional semiconductor chip and the plurality of first or second terminals of any of the plurality of subpackages so that the at least one additional semiconductor chip substitutes for the semiconductor chip of the second-type layer portion of at least one of the subpackages.

### Claim 21 (depends on 20)

The composite layered chip package according to claim 20, wherein:
the additional portion includes an additional portion main body having a top surface, a bottom surface, and four side surfaces;
the additional portion main body includes the at least one additional semiconductor chip; and
the additional portion wiring includes:
a plurality of additional portion wires that are disposed on at least one of the side surfaces of the additional portion main body;
a plurality of first additional portion terminals that are disposed on the top surface of the additional portion main body and electrically connected to the plurality of additional portion wires; and
a plurality of second additional portion terminals that are disposed on the bottom surface of the additional portion main body and electrically connected to the plurality of additional portion wires.

### Claim 22 (depends on 20)

The composite layered chip package according to claim 20, wherein the semiconductor chip in each of the layer portions and the additional semiconductor chip each include a plurality of memory cells.