# US 8,541,886 B2 · Integrated circuit packaging system with via and method of manufacture thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,541,886 B2 - Document ID: US8541886B2 - Status: Granted - Kind: B2 - Application number: 12/720,667 - Filed: 2010-03-09 - Published: 2011-09-15 - Granted: 2013-09-24 - Earliest claimed: 2010-03-09 - Assignees: STATS ChipPAC, Ltd. - Applicants: Chee Keong Chin - Inventors: Chee Keong Chin - Web page: https://patentgrep.com/patent/US8541886B2 ## CPC - H10P 72/74: {using temporarily an auxiliary support} - H10P 72/7428: {used to support diced chips prior to mounting} - H10W 72/07207: {Temporary substrates, e.g. removable substrates} - H10W 72/07236: {Soldering or alloying} - H10W 72/07251: {characterised by changes in properties of the bump connectors during connecting} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method of manufacture of an integrated circuit packaging system includes: providing a stacking carrier having a cavity; placing a base integrated circuit in the cavity, the base integrated circuit having a base interconnect facing the cavity; mounting a stack integrated circuit to the base integrated circuit; and picking the stack integrated circuit mounted to the base integrated circuit out of the stacking carrier. ## Claims ### Claim 1 A method of manufacture of an integrated circuit packaging system comprising: providing a stacking carrier having a cavity and a support step in the cavity, wherein providing the stacking carrier includes providing the stacking carrier having a compliant layer in the cavity; placing a base integrated circuit in the cavity, the base integrated circuit having a peripheral region and a base interconnect facing the cavity, the peripheral region on the support step, wherein placing the base integrated circuit in the cavity includes placing the base interconnect on the compliant layer; mounting a stack integrated circuit to the base integrated circuit; and picking the stack integrated circuit mounted to the base integrated circuit out of the stacking carrier wherein the base integrated circuit comprises the peripheral region having an impression mark characteristic of the base integrated circuit being placed on the support step. ### Claim 2 (depends on 1) The method as claimed in claim 1 wherein: providing the stacking carrier includes providing the stacking carrier having a cavity bottom below the support step; and placing the base integrated circuit in the cavity includes placing the base interconnect on the cavity bottom. ### Claim 3 (depends on 1) The method as claimed in claim 1 wherein placing the base integrated circuit in the cavity includes: providing the base integrated circuit having a protection layer surrounding the base interconnect; and placing the protection layer in contact with a cavity bottom of the cavity. ### Claim 4 A method of manufacture of an integrated circuit packaging system comprising: providing a stacking carrier having a cavity, a cavity bottom, and a support step in the cavity, the cavity bottom below the support step, wherein providing the stacking carrier includes providing the stacking carrier having a compliant layer on the cavity bottom; placing a base integrated circuit in the cavity, the base integrated circuit having a peripheral region, a gap, a base interconnect, and a through via with the base interconnect facing the cavity, the peripheral region on the support step, and the gap between the base interconnect and the cavity bottom, wherein placing the base integrated circuit in the cavity includes placing the base interconnect on the compliant layer; mounting a stack integrated circuit to the base integrated circuit, the stack integrated circuit connected to the through via; and picking the stack integrated circuit mounted to the base integrated circuit out of the stacking carrier wherein the base integrated circuit comprises the peripheral region having an impression mark characteristic of the base integrated circuit being placed on the support step. ### Claim 5 (depends on 4) The method as claimed in claim 4 wherein placing the base integrated circuit in the cavity includes placing the base integrated circuit in contact with the stacking carrier. ### Claim 6 (depends on 4) The method as claimed in claim 4 further comprising mounting the stack integrated circuit mounted to the base integrated circuit to a package carrier. ### Claim 7 An integrated circuit packaging system comprising: a base integrated circuit having a peripheral region and a base interconnect, the peripheral region having an impression mark characteristic of the base integrated circuit being placed on a support step in a cavity of a stacking carrier, wherein the base integrated circuit includes the base interconnect comprises the peripheral region having an impression mark characteristic of the base integrated circuit being placed on the support step, and having a tacky residue characteristic of a compliant layer of the stacking carrier removed from the base interconnect; and a stack integrated circuit mounted to the base integrated circuit, wherein the base base integrated circuit includes a through via, and wherein the stack integrated circuit is connected to the through via. ### Claim 8 (depends on 7) The system as claimed in claim 7 wherein the base integrated circuit having the base interconnect includes a protection layer surrounding the base interconnect. ### Claim 9 (depends on 7) The system as claimed in claim 7 wherein: the base integrated circuit includes a base terminal on the through via; and wherein the stack integrated circuit is on the base terminal. ### Claim 10 (depends on 9) The system as claimed in claim 9 further comprising: an encapsulation covering the base integrated circuit and the stack integrated circuit. ### Claim 11 (depends on 7) The system as claimed in claim 7 further comprising: a package carrier; and wherein: the stack integrated circuit mounted to the base integrated circuit is over the package carrier.