# US 8,541,885 B2 · Technique for enhancing transistor performance by transistor specific contact design

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- Number: US 8,541,885 B2
- Document ID: US8541885B2
- Status: Granted
- Kind: B2
- Application number: 13/107,515
- Filed: 2011-05-13
- Published: 2011-09-08
- Granted: 2013-09-24
- Earliest claimed: 2007-04-30
- Assignees: Globalfoundries Inc.
- Applicants: Martin Gerhardt; Ralf Richter; Thomas Feudel; Uwe Griebenow
- Inventors: Martin Gerhardt; Ralf Richter; Thomas Feudel; Uwe Griebenow
- Web page: https://patentgrep.com/patent/US8541885B2

## CPC

- H10D 30/791: {Arrangements for exerting mechanical stress on the crystal lattice of the channel regions}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D 30/0212: {using self-aligned silicidation}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

By locally adapting the size and/or density of a contact structure, for instance, within individual transistors or in a more global manner, the overall performance of advanced semiconductor devices may be increased. Hence, the mutual interaction between the contact structure and local device characteristics may be taken into consideration. On the other hand, a high degree of compatibility with conventional process strategies may be maintained.

## Claims

### Claim 1

A semiconductor device, comprising:
a P-channel transistor having a drain region and a source region;
a N-channel transistor having a drain region and a source region;
an interlayer dielectric material covering said P-channel and said N-channel transistors;
a first contact structure connecting to said drain region and source region of the P-channel transistor and comprising contact elements extending through said interlayer dielectric material, said first contact structure designed according to a first layout defined by lateral target dimensions of the contact elements and target distances between the contact elements; and
a second contact structure connecting to said drain region and said source region of the N-channel transistor and comprising contact elements extending through said interlayer dielectric material, said second contact structure designed according to a second layout defined by lateral target dimensions of the contact elements and target distances between the contact elements, said second layout differing from said first layout, wherein a minimum target distance of the second layout is less than a minimum target distance of the first layout.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein said interlayer dielectric material comprises:
a first dielectric layer formed above the P-channel transistor and having a first type of intrinsic stress; and
a second dielectric layer formed above the N-channel transistor and having a second type of intrinsic stress other than the first type.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein lateral target dimensions of the contact elements of the first contact structure are different for at least two of the contact elements.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein lateral target dimensions of the contact elements of the second contact structure are different for at least two of the contact elements of the second contact structure.

### Claim 5

A semiconductor device, comprising:
a P-channel transistor having a drain region and a source region;
a N-channel transistor having a drain region and a source region;
an interlayer dielectric material covering said P-channel and said N-channel transistors;
a first contact structure connecting to said drain region and source region of the P-channel transistor and comprising contact elements extending through said interlayer dielectric material, said first contact structure designed according to a first layout defined by lateral target dimensions of the contact elements and target distances between the contact elements; and
a second contact structure connecting to said drain region and said source region of the N-channel transistor and comprising contact elements extending through said interlayer dielectric material, said second contact structure designed according to a second layout defined by lateral target dimensions of the contact elements and target distances between the contact elements, said second layout differing from said first layout, wherein a minimum lateral target dimension in said first layout is less than a minimum lateral target dimension in said second layout.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein said interlayer dielectric material comprises:
a first dielectric layer formed above the P-channel transistor and having a first type of intrinsic stress; and
a second dielectric layer formed above the N-channel transistor and having a second type of intrinsic stress other than the first type.

### Claim 7 (depends on 5)

The semiconductor device of claim 5, wherein lateral target dimensions of the contact elements of the first contact structure are different for at least two of the contact elements.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein lateral target dimensions of the contact elements of the second contact structure are different for at least two of the contact elements of the second contact structure.