# US 8,541,881 B2 · Package structure and manufacturing method thereof

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- Number: US 8,541,881 B2
- Document ID: US8541881B2
- Status: Granted
- Kind: B2
- Application number: 13/186,448
- Filed: 2011-07-19
- Published: 2012-11-22
- Granted: 2013-09-24
- Earliest claimed: 2011-05-20
- Assignees: Subtron Technology Co., Ltd.
- Applicants: Shih-Hao Sun
- Inventors: Shih-Hao Sun
- Web page: https://patentgrep.com/patent/US8541881B2

## CPC

- H10W 74/01: Manufacture or treatment
- H10H 20/8582: {characterised by their shape}
- H10H 20/8506: {Containers}
- H10H 20/8581: {characterised by their material}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS

## Abstract

A manufacturing method of a package structure is provided. A seed layer is formed on a upper surface of a metal substrate. A patterned dry film layer is formed on a lower surface of the metal substrate and the seed layer. A portion of the seed layer is exposed by the patterned dry film layer. The patterned dry film layer is used as an electroplating mask to electroplate a circuit layer on the portion of the seed layer exposed by the patterned dry film layer. A chip is bonded to and electrically connected to the circuit layer. A molding compound is formed on the metal substrate. The molding compound encapsulates the chip, the circuit layer and the portion of the seed layer. A portion of the metal substrate and a portion of the seed layer are removed so as to expose a portion of the molding compound.

## Claims

### Claim 1

A package structure, comprising:
a metal substrate having an upper surface and a lower surface opposite to each other and a plurality of openings connecting the upper surface and the lower surface;
a circuit layer disposed on the upper surface of the metal substrate;
a chip disposed on the circuit layer and electrically connected to the circuit layer; and
a molding compound encapsulating the chip and the circuit layer, wherein a bottom surface of the molding compound substantially aligns with the upper surface of the metal substrate, and the openings of the metal substrate expose a portion of the bottom surface of the molding compound.

### Claim 2 (depends on 1)

The package structure as claimed in claim 1, further comprising:
a surface treatment layer disposed on the circuit layer; and
a seed layer disposed on the upper surface of the metal substrate and sandwiched between the circuit layer and the metal substrate.

### Claim 3

A package structure, comprising:
a insulation layer having an upper surface and a lower surface opposite to each other and a plurality of openings connecting the upper surface and the lower surface;
a circuit layer disposed on the top surface of the insulation layer, arranged on top of the openings correspondingly, and exposing a portion of the top surface;
a first metal layer disposed on the bottom surface of the insulation layer and exposing a portion of the top surface and the openings;
a second metal layer disposed in the openings of the insulation layer and connecting the circuit layer and the first metal layer, wherein a side of the second metal layer substantially aligns with the top surface of the insulation layer;
a chip disposed on the circuit layer and electrically connected to the circuit layer; and
a molding compound encapsulating the chip and the circuit layer and covering the portion of the top surface of the insulation layer.

### Claim 4 (depends on 3)

The package structure as claimed in claim 3, further comprising:
a surface treatment layer disposed on the circuit layer; and
a seed layer disposed among the circuit layer, the second metal layer and a portion of the insulation layer.