# US 8,541,879 B2 · Super-self-aligned contacts and method for making the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,541,879 B2
- Document ID: US8541879B2
- Status: Granted
- Kind: B2
- Application number: 11/956,305
- Filed: 2007-12-13
- Published: 2009-06-18
- Granted: 2013-09-24
- Earliest claimed: 2007-12-13
- Assignees: Tela Innovations, Inc.
- Applicants: Michael C. Smayling
- Inventors: Michael C. Smayling
- Web page: https://patentgrep.com/patent/US8541879B2

## CPC

- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/663: {the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 89/10: Integrated device layouts
- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/071: {of dielectric parts thereof}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10P 50/73: {using masks for insulating materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A number of first hard mask portions are formed on a dielectric layer to vertically shadow a respective one of a number of underlying gate structures. A number of second hard mask filaments are formed adjacent to each side surface of each first hard mask portion. A width of each second hard mask filament is set to define an active area contact-to-gate structure spacing. A first passage is etched between facing exposed side surfaces of a given pair of neighboring second hard mask filaments and through a depth of the semiconductor wafer to an active area. A second passage is etched through a given first hard mask portion and through a depth of the semiconductor wafer to a top surface of the underlying gate structure. An electrically conductive material is deposited within both the first and second passages to respectively form an active area contact and a gate contact.

## Claims

### Claim 1

A semiconductor device, comprising:
a linear gate structure having side surfaces and a top surface, wherein a width of the linear gate structure is defined by a perpendicular distance between the side surfaces;
a gate contact disposed to electrically connect to the top surface of the linear gate structure, wherein the gate contact has a substantially rectangular horizontal cross-section, and wherein the gate contact is defined to substantially cover the width of the linear gate structure without extending substantially beyond either of the side surfaces of the linear gate structure; and
a photon absorption layer disposed adjacent to the side surfaces of the linear gate structure so as to contact the side surfaces of the linear gate structure without covering the top surface of the linear gate structure.

### Claim 2 (depends on 1)

A semiconductor device as recited in claim 1, wherein the top surface of the linear gate structure is formed from a photon reflecting material.

### Claim 3 (depends on 1)

A semiconductor device as recited in claim 1, wherein the photon absorption layer is disposed to fill regions adjacent to the linear gate structure.

### Claim 4 (depends on 1)

A semiconductor device as recited in claim 1, further comprising:
a dielectric layer disposed over both the photon absorption layer and the linear gate structure, wherein the dielectric layer includes a passage through which the gate contact is disposed, and wherein the passage is defined by a substantially rectangular horizontal cross-section along its length.

### Claim 5 (depends on 1)

A semiconductor device as recited in claim 1, further comprising:
a pair of linear gate structures disposed parallel to each other, each of the pair of linear gate structures having side surfaces and a top surface; and
an active area contact disposed to electrically connect to an active area present between facing side surfaces of the pair of linear gate structures, wherein the active area contact has a substantially rectangular horizontal cross-section, and wherein the active area contact is disposed to be substantially centered between facing side surfaces of the pair of linear gate structures.

### Claim 6

A semiconductor device, comprising:
a linear gate structure having side surfaces and a top surface, the linear gate structure extending lengthwise in a first direction, wherein a length of the linear gate structure as measured in the first direction is larger than a width of the linear gate structure as measured in a second direction perpendicular to the first direction;
sidewall spacers formed on the side surfaces of the linear gate structure; and
a gate contact disposed to electrically connect to the top surface of the linear gate structure, the gate contact having a substantially rectangular horizontal cross-section, the gate contact defined to substantially cover the width of the linear gate structure without extending substantially beyond either of the side surfaces of the linear gate structure, the gate contact having a first dimension as measured in the first direction that is larger than a second dimension as measured in the second direction, and the gate contact confined within a vertical region between the sidewall spacers above the linear gate structure.

### Claim 7 (depends on 6)

A semiconductor device as recited in claim 6, further comprising:
a photon absorption layer disposed adjacent to the side surfaces of the linear gate structure so as to contact the side surfaces of the linear gate structure without covering the top surface of the linear gate structure.

### Claim 8 (depends on 7)

A semiconductor device as recited in claim 7, wherein the photon absorption layer is disposed to fill regions adjacent to the linear gate structure.

### Claim 9 (depends on 7)

A semiconductor device as recited in claim 7, further comprising:
a dielectric layer disposed over both the photon absorption layer and the linear gate structure, wherein the dielectric layer includes a passage through which the gate contact is disposed, and wherein the passage is defined by a substantially rectangular horizontal cross-section along its length.

### Claim 10 (depends on 6)

A semiconductor device as recited in claim 6, wherein the top surface of the linear gate structure is formed from a photon reflecting material.

### Claim 11 (depends on 6)

A semiconductor device as recited in claim 6, further comprising:
a pair of linear gate structures disposed parallel to each other, each of the pair of linear gate structures having side surfaces and a top surface; and
an active area contact disposed to electrically connect to an active area present between facing side surfaces of the pair of linear gate structures, wherein the active area contact has a substantially rectangular horizontal cross-section, and wherein the active area contact is disposed to be substantially centered between facing side surfaces of the pair of linear gate structures.

### Claim 12

A semiconductor device, comprising:
a pair of linear gate structures disposed parallel to each other, each of the pair of linear gate structures having side surfaces and a top surface, each of the pair of linear gate structures extending lengthwise in a first direction, wherein a length and a width of each of the pair of linear gate structures are such that the length as measured in the first direction is larger than the width as measured in a second direction perpendicular to the first direction;
a gate contact disposed to electrically connect to the top surface of at least one of the pair of linear gate structures, the gate contact having a substantially rectangular horizontal cross-section, the gate contact defined to substantially cover the width of the linear gate structure to which it connects without extending substantially beyond either of the side surfaces of the linear gate structure to which it connects, the gate contact having a first dimension as measured in the first direction that is larger than a second dimension as measured in the second direction; and
an active area contact disposed to electrically connect to an active area present between facing side surfaces of the pair of linear gate structures, wherein the active area contact has a substantially rectangular horizontal cross-section, and wherein the active area contact is disposed to be substantially centered between facing side surfaces of the pair of linear gate structures.

### Claim 13 (depends on 12)

A semiconductor device as recited in claim 12, further comprising:
a photon absorption layer disposed adjacent to the side surfaces of each of the pair of linear gate structures so as to contact the side surfaces of each of the pair of linear gate structures without covering the top surfaces of the pair of linear gate structures.

### Claim 14 (depends on 13)

A semiconductor device as recited in claim 13, wherein the photon absorption layer is disposed to fill regions adjacent to each of the pair of linear gate structures.

### Claim 15 (depends on 13)

A semiconductor device as recited in claim 13, further comprising:
a dielectric layer disposed over both the photon absorption layer and the pair of linear gate structures, wherein the dielectric layer includes a passage through which the gate contact is disposed, and wherein the passage is defined by a substantially rectangular horizontal cross-section along its length.

### Claim 16 (depends on 12)

A semiconductor device as recited in claim 12, wherein the top surfaces of the pair of linear gate structures are formed from a photon reflecting material.