# US 8,541,877 B2 · Electronic device package and method for fabricating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,541,877 B2 - Document ID: US8541877B2 - Status: Granted - Kind: B2 - Application number: 12/849,089 - Filed: 2010-08-03 - Published: 2011-06-16 - Granted: 2013-09-24 - Earliest claimed: 2009-12-16 - Applicants: Chia-Lun Tsai; Ching-Yu Ni; Tien-Hao Huang; Chia-Ming Cheng; Wen-Cheng Chien; Nan-Chun Lin; Wei-Ming Chen; Shu-Ming Chang; Bai-Yao Lou - Inventors: Chia-Lun Tsai; Ching-Yu Ni; Tien-Hao Huang; Chia-Ming Cheng; Wen-Cheng Chien; Nan-Chun Lin; Wei-Ming Chen; Shu-Ming Chang; Bai-Yao Lou - Web page: https://patentgrep.com/patent/US8541877B2 ## CPC - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/68: Shapes or dispositions thereof - H10W 74/114: {by a substrate and the encapsulations} - H10W 46/301: {for alignment} - H10W 46/601: {for use after dicing} - H10W 46/607: {Located on parts of packages, e.g. on encapsulations or on package substrates} - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/656: Fan-in layouts - H10W 70/682: {comprising holes having chips therein} - H10W 72/073: {of die-attach connectors} - H10W 72/07323: {Active alignment, e.g. using optical alignment using marks or sensors} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/874: {On different surfaces} - H10W 72/9413: {on encapsulations} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 99/00: Subject matter not provided for in other groups of this subclass - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract The invention provides an electronic device package and a method for fabricating the same. The electronic device package includes a carrier wafer. An electronic device chip with a plurality of conductive pads thereon is disposed over the carrier wafer. An isolation laminating layer includes a lower first isolation layer, which covers the carrier wafer and the electronic device chip, and an upper second isolation layer. The isolation laminating layer has a plurality of openings to expose the conductive pads. A plurality of redistribution patterns is conformably formed on the isolation laminating layer and in the openings. The redistribution patterns are electrically connected to the conductive pads, respectively. A plurality of conductive bumps is respectively formed on the redistribution patterns, electrically connected to the conductive pads. ## Claims ### Claim 1 An electronic device package, comprising: a carrier wafer; an electronic device chip disposed over the carrier wafer, wherein the electronic device chip has a plurality of conductive pads disposed thereon; an isolation combo layer comprising a lower first isolation layer, which covers the carrier wafer and the electronic device chip, and an upper second isolation layer, wherein the lower first isolation layer has a plurality of first openings to expose the plurality of conductive pads, and the upper second isolation layer conformably covers the lower first isolation layer and inner walls of the first openings, wherein the upper second isolation layer located in the first openings has a plurality of second openings respectively located in the first openings to expose the plurality of conductive pads; a plurality of redistribution patterns isolated from each other conformably formed on the isolation combo layer and in the first openings and the second openings, electrically connecting to the plurality of conductive pads, respectively; and a plurality of conductive bumps respectively formed on the plurality of redistribution patterns, electrically connecting to the plurality of conductive pads. ### Claim 2 (depends on 1) The electronic device package as claimed in claim 1, further comprising a protection layer covering a portion of the plurality of redistribution patterns. ### Claim 3 (depends on 1) The electronic device package as claimed in claim 1, wherein the first isolation layer is a dry film photoresist. ### Claim 4 (depends on 1) The electronic device package as claimed in claim 1, wherein the first isolation layer further comprises a silica particle therein. ### Claim 5 (depends on 1) The electronic device package as claimed in claim 1, wherein the second isolation layer comprises epoxy resin, solder mask layers, silicon oxide layers, silicon nitride layers, silicon oxynitride layers, metal oxides, polyimide, butylcyclobutene (BCB), parylene, polynaphthalenes, fluorocarbons, accrylates or combinations thereof. ### Claim 6 (depends on 1) The electronic device package as claimed in claim 1, wherein the carrier wafer has a cavity, and the electronic device chip is disposed in the cavity. ### Claim 7 (depends on 6) The electronic device package as claimed in claim 6, wherein the first isolation layer fills the cavity, covering a top surface of the carrier wafer. ### Claim 8 (depends on 6) The electronic device package as claimed in claim 6, wherein a top surface of the carrier wafer adjacent to the cavity has an alignment pattern thereon. ### Claim 9 (depends on 1) The electronic device package as claimed in claim 1, wherein a thickness of the first isolation layer is larger than that of the second isolation layer. ### Claim 10 (depends on 1) The electronic device package as claimed in claim 1, wherein each of the plurality of first openings exposes at least one the conductive pad. ### Claim 11 (depends on 1) The electronic device package as claimed in claim 1, wherein the conductive bumps electrically connected to any adjacent two of the conductive pads are respectively disposed inside and outside of the electronic device chip. ### Claim 12 (depends on 1) The electronic device package as claimed in claim 1, wherein a coefficient of viscosity of the second isolation layer is lower than that of the first isolation layer. ### Claim 13 (depends on 1) The electronic device package as claimed in claim 1, wherein a mechanical strength of the first isolation layer is larger than that of the second isolation layer. ### Claim 14 An electronic device package, comprising: a carrier wafer; an electronic device chip disposed over the carrier wafer, wherein the electronic device chip has a plurality of conductive pads disposed thereon; an isolation combo layer comprising a lower first isolation layer, which covers the carrier wafer and the electronic device chip, and an upper second isolation layer, wherein the lower first isolation layer has a plurality of first openings to expose the plurality of conductive pads, and the upper second isolation layer conformably covers the lower first isolation layer and inner walls of the first openings, wherein the upper second isolation layer located in the first openings has a plurality of second openings respectively located in the first openings to expose the plurality of conductive pads; a plurality of redistribution patterns isolated from each other conformably formed on the isolation combo layer and in the openings, electrically connecting to the plurality of conductive pads, respectively; and a plurality of conductive bumps respectively formed on the plurality of redistribution patterns, electrically connecting to the plurality of conductive pads, wherein there is no any redistribution pattern located between the lower first isolation layer and the upper second isolation layer. ### Claim 15 (depends on 14) The electronic device package as claimed in claim 14, further comprising a protection layer covering a portion of the plurality of redistribution patterns. ### Claim 16 (depends on 14) The electronic device package as claimed in claim 14, wherein the first isolation layer is a dry film photoresist. ### Claim 17 (depends on 14) The electronic device package as claimed in claim 14, wherein the first isolation layer further comprises a silica particle therein. ### Claim 18 (depends on 14) The electronic device package as claimed in claim 14, wherein the second isolation layer comprises epoxy resin, solder mask layers, silicon oxide layers, silicon nitride layers, silicon oxynitride layers, metal oxides, polyimide, butylcyclobutene (BCB), parylene, polynaphthalenes, fluorocarbons, accrylates or combinations thereof. ### Claim 19 (depends on 14) The electronic device package as claimed in claim 14, wherein the carrier wafer has a cavity, and the electronic device chip is disposed in the cavity. ### Claim 20 (depends on 19) The electronic device package as claimed in claim 19, wherein the first isolation layer fills the cavity, covering a top surface of the carrier wafer. ### Claim 21 (depends on 19) The electronic device package as claimed in claim 19, wherein a top surface of the carrier wafer adjacent to the cavity has an alignment pattern thereon. ### Claim 22 (depends on 14) The electronic device package as claimed in claim 14, wherein a thickness of the first isolation layer is larger than that of the second isolation layer. ### Claim 23 (depends on 14) The electronic device package as claimed in claim 14, wherein each of the plurality of openings exposes at least one the conductive pad. ### Claim 24 (depends on 14) The electronic device package as claimed in claim 14, wherein the conductive bumps electrically connected to any adjacent two of the conductive pads are respectively disposed inside and outside of the electronic device chip. ### Claim 25 (depends on 14) The electronic device package as claimed in claim 14, wherein a coefficient of viscosity of the second isolation layer is lower than that of the first isolation layer. ### Claim 26 (depends on 14) The electronic device package as claimed in claim 14, wherein a mechanical strength of the first isolation layer is larger than that of the second isolation layer.