# US 8,541,874 B2 · Semiconductor device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,541,874 B2
- Document ID: US8541874B2
- Status: Granted
- Kind: B2
- Application number: 13/495,494
- Filed: 2012-06-13
- Published: 2012-10-04
- Granted: 2013-09-24
- Earliest claimed: 2004-06-30
- Assignees: Renesas Electronics Corporation
- Applicants: Yoichiro Kurita
- Inventors: Yoichiro Kurita
- Web page: https://patentgrep.com/patent/US8541874B2

## CPC

- H10W 90/00: Package configurations
- H10W 20/42: Vias, e.g. via plugs
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/856: {Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15)}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/20: Configurations of stacked chips
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/721: {of bump connectors}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113, and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101. The interconnect component 101 has a constitution where an interconnect layer 103, a silicon layer 105 and an insulating film 107 are sequentially formed. The interconnect layer 103 has a constitution where the interconnect layer 103 has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element 113 is electrically connected with the second semiconductor element 111 through the conductive component.

## Claims

### Claim 1

A semiconductor device comprising:
a first memory chip having a main surface, a first electrode and a second electrode on the main surface;
a second memory chip having a third electrode, a fourth electrode, a first electrode penetrating the second memory chip and a second through electrode penetrating the second memory chip;
a logic chip having a first side, a second side opposite the first side, a fifth electrode, a sixth electrode, a seventh electrode and an eighth electrode;
the first memory chip stacked over the second memory chip;
the logic chip formed under the second memory chip;
the first electrode electrically connecting to the first through electrode;
the second electrode electrically connecting to the second through electrode;
the first through electrode electrically connecting to the third electrode;
the second through electrode electrically connecting to the fourth electrode;
the third electrode electrically connecting to the fifth electrode;
the fourth electrode electrically connecting to the sixth electrode;
the fifth electrode and the sixth electrode arrayed in a central area of the logic chip in a cross sectional view;
the seventh electrode arrayed along the first side of the logic chip in the cross section view; and
the eighth electrode arrayed along the second side of the logic chip in the cross section view,
wherein a pitch between the first electrode and the second electrode is equal to a pitch between the fifth electrode and the sixth electrode, and
a pitch between the seventh electrode and the eighth electrode is wider than the pitch between the fifth electrode and the sixth electrode.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the first electrode, the first through electrode, the third electrode and the fifth electrode are formed in line along a normal line to the main surface of the first memory chip in cross sectional view, and
the second electrode, the second through electrode, the fourth electrode and the sixth electrode are formed in line along a normal line to the main surface of the first memory chip in cross sectional view.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1,
wherein the first electrode and the second electrode are arrayed in a central area of the first memory chip in cross sectional view, and
the third electrode, the fourth electrode, the first through electrode and the second through electrode are arrayed in the central area of the second memory chip in cross sectional view.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1,
wherein the fifth electrode and the sixth electrode are arranged in a minimal interval of not more than 50 μm.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, further comprising:
an interconnect component mounting the logic chip;
the interconnect component including wirings and a plurality of external electrodes; and
the plurality of external electrodes including a first external electrode and a second external electrode,
wherein the first external electrode is electrically connected to the seventh electrode of the logic chip via the wirings, and
the second external electrode is electrically connected to the eighth electrode of the logic chip via the wirings.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5, wherein the logic chip and the interconnect component are connected by a flip-chip connection.

### Claim 7 (depends on 5)

The semiconductor device according to claim 5, further comprising:
a first underfill resin filling between the interconnect component and the logic chip.

### Claim 8 (depends on 7)

The semiconductor device according to claim 7, further comprising:
a second underfill resin filling between the interconnect component and the second memory chip; and
a third underfill resin filling between the second memory and the first memory chip.

### Claim 9 (depends on 8)

The semiconductor device according to claim 8, further comprising:
a sealing resin covering a surface of said interconnect component, the second underfill resin, the third underfill resin and the first memory chip and the second memory chip.