# US 8,541,873 B2 · Microelectronic packages having cavities for receiving microelectronic elements

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- Number: US 8,541,873 B2
- Document ID: US8541873B2
- Status: Granted
- Kind: B2
- Application number: 13/205,162
- Filed: 2011-08-08
- Published: 2011-12-01
- Granted: 2013-09-24
- Earliest claimed: 2007-04-16
- Assignees: Tessera, Inc.
- Applicants: Ilyas Mohammed; Belgacem Haba; Wael Zohni; Philip R. Osborn
- Inventors: Ilyas Mohammed; Belgacem Haba; Wael Zohni; Philip R. Osborn
- Web page: https://patentgrep.com/patent/US8541873B2

## CPC

- H10W 72/50: Bond wires
- H10W 20/42: Vias, e.g. via plugs
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 90/00: Package configurations
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/682: {comprising holes having chips therein}
- H10W 70/685: comprising multiple insulating layers
- H10W 72/07251: {characterised by changes in properties of the bump connectors during connecting}
- H10W 72/07352: {changes in structures or sizes}
- H10W 72/075: {of bond wires}
- H10W 72/07554: {changes in dispositions}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/251: {Materials}
- H10W 72/321: {Structures or relative sizes of die-attach connectors}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/865: {Die-attach connectors and bond wires}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/9223: {with redistribution layers [RDL]}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Packaged microelectronic elements are provided which include a dielectric element, a cavity, a plurality of chip contacts and a plurality of package contacts, and microelectronic elements having a plurality of bond pads connected to the chip contacts.

## Claims

### Claim 1

A packaged microelectronic element, comprising:
a package element, said package element including:
a first dielectric element having a bottom face and a top face remote from said bottom face;
a plurality of package contacts and a plurality of first chip contacts exposed at said top face, said first chip contacts being connected to said package contacts,
a second dielectric element having a bottom face adjacent to said package contacts and a top face remote from said bottom face, said second dielectric element overlying said top face of said first dielectric element and having openings aligned with said package contacts;
a plurality of second chip contacts exposed at said bottom face of said second dielectric element;
a first microelectronic element having a plurality of bond pads connected to said chip contacts; and
a second microelectronic element having bond pads connected to said second chip contacts.

### Claim 2 (depends on 1)

The packaged microelectronic element of claim 1, wherein said microelectronic element further comprises a front face and a rear face, wherein said bond pads are exposed at said front face of the microelectronic element, and wherein bond wires connect said bond pads to said chip contacts.

### Claim 3 (depends on 1)

The packaged microelectronic element of claim 1, wherein said dielectric element has edges extending between said top and bottom faces, said edges being joined at corners, and corner regions at said corners having first width in a first direction interconnected by strip regions having a second width in said first direction smaller than said first width, wherein said package contacts are exposed at said corner regions.

### Claim 4 (depends on 1)

The packaged microelectronic element of claim 1, wherein said first dielectric element has an inner edge extending between said top and bottom faces, said inner edge defining an opening.

### Claim 5 (depends on 4)

The packaged microelectronic element of claim 4, wherein said inner edge of said first opening extends beyond said inner edge of said second opening is a ledge.

### Claim 6 (depends on 5)

The packaged microelectronic element of claim 5, wherein at least one of said plurality of chip contacts is exposed on said ledge.

### Claim 7 (depends on 4)

The packaged microelectronic element of claim 4, wherein said opening is a first opening and said second dielectric element has an inner edge extending between said top and bottom faces, said inner edge of said second dielectric element defining a second opening aligned with said first opening.

### Claim 8 (depends on 7)

The packaged microelectronic element of claim 7, wherein said first and second openings define an interior cavity of said packaged microelectronic element.

### Claim 9 (depends on 7)

The packaged microelectronic element of claim 7, wherein said inner edge of said first opening extends beyond said inner edge of said second opening.

### Claim 10 (depends on 8)

The packaged microelectronic element of claim 8, wherein said interior cavity is in the shape of a cross.

### Claim 11 (depends on 8)

The packaged microelectronic element of claim 8, wherein said interior cavity is in the shape of a rectangle.

### Claim 12 (depends on 1)

The packaged microelectronic element of claim 1, further comprising openings extending through said second dielectric element.

### Claim 13 (depends on 1)

The packaged microelectronic element of claim 1, wherein said package contacts on said top face of said first dielectric element are aligned with said openings.

### Claim 14 (depends on 8)

The packaged microelectronic element of claim 8, wherein said microelectronic element is laterally adjacent said packaged element.

### Claim 15 (depends on 1)

The packaged microelectronic element of claim 1, wherein said interior cavity of said packaged microelectronic element has interior projections and wherein said packaged microelectronic element further comprises a metal shelf disposed over said interior projections.

### Claim 16 (depends on 15)

The packaged microelectronic element of claim 15, wherein said microelectronic element has a top surface and a bottom surface and said metal shelf has a top surface and a bottom surface, said bottom surface of said microelectronic element attached to said top surface of said metal shelf.