# US 8,541,872 B2 · Integrated circuit package system with package stacking and method of manufacture thereof

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- Number: US 8,541,872 B2
- Document ID: US8541872B2
- Status: Granted
- Kind: B2
- Application number: 12/791,867
- Filed: 2010-06-02
- Published: 2011-12-08
- Granted: 2013-09-24
- Earliest claimed: 2010-06-02
- Assignees: STATS ChipPAC, Ltd.
- Applicants: NamJu Cho; HeeJo Chi; HanGil Shin
- Inventors: NamJu Cho; HeeJo Chi; HanGil Shin
- Web page: https://patentgrep.com/patent/US8541872B2

## CPC

- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/421: {Shapes or dispositions}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/00: Package configurations
- H10W 90/811: {Multiple chips on leadframes}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/68: Shapes or dispositions thereof
- H10W 70/681: {comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/30: Die-attach connectors
- H10W 72/865: {Die-attach connectors and bond wires}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/721: {of bump connectors}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacture of an integrated circuit package system includes: forming a non-inverted internal stacking module including: fabricating an internal stacking module (ISM) substrate having an ISM component side and an ISM coupling side, coupling an internal stacking module integrated circuit to the ISM component side, coupling stacking structures, adjacent to the internal stacking module integrated circuit, on the ISM component side, and molding a stacking module body having a top surface that is coplanar with and exposes the stacking structures; forming a base package substrate under the non-inverted internal stacking module; coupling middle structures between the base package substrate and the ISM coupling side; and forming a base package body on the base package substrate, the middle structures, and the non-inverted internal stacking module including exposing the top surface of the stacking module body to be coplanar with the base package body.

## Claims

### Claim 1

A method of manufacture of an integrated circuit package system comprising:
forming a non-inverted internal stacking module including:
fabricating an internal stacking module (ISM) substrate having an ISM component side and an ISM coupling side,
coupling an internal stacking module integrated circuit to the ISM component side,
coupling stacking structures, adjacent to the internal stacking module integrated circuit, on the ISM component side, and
molding a stacking module body having a top surface that is coplanar with and exposes the stacking structures;
forming a base package substrate under the non-inverted internal stacking module;
coupling middle structures between the base package substrate and the ISM coupling side; and
forming a base package body on the base package substrate, the middle structures, the ISM coupling side, the stacking module body, and the non-inverted internal stacking module, the base package body having a top surface coplanar with the top surface of the stacking module body and a top stacking surface of the stacking structures.

### Claim 2 (depends on 1)

The method as claimed in claim 1 further comprising coupling a base integrated circuit die on the base package substrate surrounded by the middle structures.

### Claim 3 (depends on 1)

The method as claimed in claim 1 wherein fabricating the internal stacking module substrate includes forming an opening in the internal stacking module substrate.

### Claim 4 (depends on 1)

The method as claimed in claim 1 further comprising coupling a stacked integrated circuit package on the stacking structures.

### Claim 5 (depends on 1)

The method as claimed in claim 1 further comprising coupling a second internal stacking module integrated circuit over the internal stacking module integrated circuit.

### Claim 6

A method of manufacture of an integrated circuit package system comprising:
forming a non-inverted internal stacking module including:
fabricating an internal stacking module (ISM) substrate having an ISM component side and an ISM coupling side including forming connection pads on the ISM component side and coupling pads on the ISM coupling side,
coupling an internal stacking module integrated circuit to the ISM component side including coupling electrical interconnects between the internal stacking module integrated circuit and the connection pads,
coupling stacking structures, adjacent to the internal stacking module integrated circuit, on the ISM component side by the stacking structures coupled to the connection pads, and
molding a stacking module body having a top surface that is coplanar with and exposes the stacking structures;
forming a base package substrate under the non-inverted internal stacking module including the base package substrate is larger than the non-inverted internal stacking module;
coupling middle structures between the base package substrate and the ISM coupling side including coupling conductive columns, conductive pillars, or conductive balls;
and
forming a base package body on the base package substrate, the middle structures, the ISM coupling side, the stacking module body, and the non-inverted internal stacking module, the base package body having a top surface coplanar with the top surface of the stacking module body and a top stacking surface of the stacking structures.

### Claim 7 (depends on 6)

The method as claimed in claim 6 further comprising coupling a base integrated circuit die on the base package substrate surrounded by the middle structures including applying an adhesive between the base integrated circuit die and the base package substrate.

### Claim 8 (depends on 6)

The method as claimed in claim 6 wherein fabricating the internal stacking module substrate includes forming an opening in the internal stacking module substrate; and
further comprising:
mounting a second base integrated circuit die over the base integrated circuit die wherein the second base integrated circuit die protrudes into the opening in the internal stacking module substrate.

### Claim 9 (depends on 6)

The method as claimed in claim 6 further comprising coupling a stacked integrated circuit package on the stacking structures including coupling a multi-chip integrated circuit package, an integrated circuit carrier, or a Quad Flatpack No lead package.

### Claim 10 (depends on 6)

The method as claimed in claim 6 further comprising coupling a second internal stacking module integrated circuit over the internal stacking module integrated circuit including forming a protruding region in the center of the top surface.

### Claim 11

An integrated circuit package system comprising:
a non-inverted internal stacking module including:
an internal stacking module (ISM) substrate having an ISM component side and an ISM coupling side,
an internal stacking module integrated circuit coupled to the ISM component side,
stacking structures, adjacent to the internal stacking module integrated circuit, coupled on the ISM component side, and
a stacking module body having a top surface that is coplanar with and exposes the stacking structures;
a base package substrate under the non-inverted internal stacking module;
middle structures coupled between the base package substrate and the ISM coupling side; and
a base package body on the base package substrate, the middle structures, the ISM coupling side, the stacking module body, and the non-inverted internal stacking module, the base package body having a top surface coplanar with the top surface of the stacking module body and a top stacking surface of the stacking structures.

### Claim 12 (depends on 11)

The system as claimed in claim 11 further comprising a base integrated circuit die on the base package substrate surrounded by the middle structures.

### Claim 13 (depends on 11)

The system as claimed in claim 11 wherein the internal stacking module substrate includes an opening formed in the internal stacking module substrate.

### Claim 14 (depends on 11)

The system as claimed in claim 11 further comprising a stacked integrated circuit package on the stacking structures.

### Claim 15 (depends on 11)

The system as claimed in claim 11 further comprising a second internal stacking module integrated circuit over the internal stacking module integrated circuit.

### Claim 16 (depends on 11)

The system as claimed in claim 11 further comprising:
connection pads on the ISM component side and coupling pads on the ISM coupling side of the internal stacking module substrate;
electrical interconnects coupled between the internal stacking module integrated circuit and the connection pads; and
conductive columns, conductive pillars, or conductive balls coupled between the base package substrate and the internal stacking module substrate.

### Claim 17 (depends on 16)

The system as claimed in claim 16 further comprising a base integrated circuit die on the base package substrate surrounded by the middle structures includes an adhesive between the base integrated circuit die and the base package substrate.

### Claim 18 (depends on 16)

The system as claimed in claim 16 wherein the internal stacking module substrate includes an opening formed in the internal stacking module substrate; and
further comprising:
a second base integrated circuit die over the base integrated circuit die wherein the second base integrated circuit die protrudes into the opening in the internal stacking module substrate.

### Claim 19 (depends on 16)

The system as claimed in claim 16 further comprising a stacked integrated circuit package on the stacking structures includes a multi-chip integrated circuit package, an integrated circuit carrier, or a Quad Flatpack No lead package.

### Claim 20 (depends on 16)

The system as claimed in claim 16 further comprising a second internal stacking module integrated circuit over the internal stacking module integrated circuit includes a protruding region in the center surrounded by the top surface.