# US 8,541,868 B2 · Top electrode templating for DRAM capacitor

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- Number: US 8,541,868 B2
- Document ID: US8541868B2
- Status: Granted
- Kind: B2
- Application number: 13/665,524
- Filed: 2012-10-31
- Published: 2013-05-16
- Granted: 2013-09-24
- Earliest claimed: 2011-11-11
- Assignees: Intermolecular, Inc.; Elpida Memory, Inc.
- Applicants: Intermolecular, Inc.; Elpida Memory, Inc
- Inventors: Sandra G. Malhotra; Hanhong Chen; Wim Y. Deweerd; Hiroyuki Ode
- Web page: https://patentgrep.com/patent/US8541868B2

## CPC

- H10D 1/68: Capacitors having no potential barriers
- H10B 12/033: {the capacitor extending over the transistor}
- H10D 1/696: {comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688)}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/6506: {Formation of intermediate materials}
- H10P 14/6544: {to change the morphology of the insulating materials, e.g. transformation of an amorphous layer into a crystalline layer}
- H10P 14/69394: {the material containing titanium, e.g. TiO2}
- H10P 14/69397: {the material containing two or more metal elements}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. A metal oxide second electrode layer is formed above the dielectric layer. The metal oxide second electrode layer has a crystal structure that is compatible with the crystal structure of the dielectric layer. Optionally, a second electrode bulk layer is formed above the metal oxide second electrode layer.

## Claims

### Claim 1

A semiconductor layer stack comprising:
a first electrode layer formed above a substrate;
a dielectric layer formed above the first electrode layer
wherein the dielectric layer has a rutile crystal structure; and
a metal oxide second electrode layer formed above the dielectric layer,
wherein the metal oxide second electrode layer comprises molybdenum oxide having a rutile or distorted rutile crystal structure,
wherein the metal oxide second electrode layer and the dielectric layer have reverse templating crystal structure compatibility such that the metal oxide second electrode layer exhibits a structural synergy by interfacing with the dielectric layer.

### Claim 2 (depends on 1)

The semiconductor layer stack of claim 1 wherein a lattice parameter of the metal oxide second electrode layer is within about 10% of an associated lattice parameter of the dielectric layer.

### Claim 3 (depends on 1)

The semiconductor layer stack of claim 1 wherein the first electrode layer comprises one of a metal, a metal alloy, a conductive metal oxide, a conductive metal silicide, a conductive metal carbide, a conductive metal nitride, or combinations thereof.

### Claim 4 (depends on 3)

The semiconductor layer stack of claim 3 wherein the first electrode layer comprises one of molybdenum oxide, tungsten oxide, ruthenium oxide, iridium oxide, chromium oxide, manganese oxide, tin oxide, or cobalt oxide.

### Claim 5 (depends on 4)

The semiconductor layer stack of claim 4 wherein the first electrode layer comprises molybdenum oxide.

### Claim 6 (depends on 1)

The semiconductor layer stack of claim 1 wherein the dielectric layer comprises a dopant.

### Claim 7 (depends on 6)

The semiconductor layer stack of claim 6 wherein the dielectric layer comprises TiO2 and wherein the dopant comprises one of Al, Ce, Co, Er, Ga, Gd, Ge, Hf, In, La, Lu, Mg, Mn, Nd, Pr, Sc, Si, Sn, Sr, Y, Zr, or combinations thereof.

### Claim 8 (depends on 1)

The semiconductor layer stack of claim 1 wherein the metal oxide second electrode layer comprises one of molybdenum oxide, tungsten oxide, ruthenium oxide, iridium oxide, chromium oxide, manganese oxide, tin oxide, or cobalt oxide.

### Claim 9 (depends on 1)

The semiconductor layer stack of claim 1 wherein the dielectric layer comprises one of Al2O3, BaSrTiOx, HfO2, HfSiOx, Nb2O5, PbZrTiOx, SiO2, a bilayer of SiO2 and SixNy, SiON, SrTiO3 (STO), Ta2O5, TiO2, ZrO2, or doped versions of the same.

### Claim 10 (depends on 1)

The semiconductor layer stack of claim 1 wherein the dielectric layer comprises TiO2 doped with Al2O3.

### Claim 11 (depends on 10)

The semiconductor layer stack of claim 10, wherein a ratio of aluminum relative to a combination of aluminum and titanium (Al/(Al+Ti)) in the dielectric layer is between about 5 atomic % and about 15 atomic %.

### Claim 12 (depends on 1)

The semiconductor layer stack of claim 1 wherein the dielectric layer has a thickness of between about 6 nm and 10 nm.

### Claim 13 (depends on 1)

The semiconductor layer stack of claim 1 wherein the dielectric layer comprises a nanolaminate.

### Claim 14

A semiconductor layer stack comprising:
a first electrode layer formed above a substrate;
a dielectric layer formed above the first electrode layer,
wherein the dielectric layer has a rutile crystal structure;
a metal oxide second electrode interface layer formed above the dielectric layer,
wherein the metal oxide second electrode layer comprises molybdenum oxide having a rutile or distorted rutile crystal structure,
wherein the metal oxide second electrode layer and the dielectric layer have reverse templating crystal structure compatibility such that the metal oxide second electrode layer exhibits a structural synergy by interfacing with the dielectric layer; and
a second electrode bulk layer formed above the metal oxide second electrode interface layer.

### Claim 15 (depends on 14)

The semiconductor layer stack of claim 14 wherein a lattice parameter of the metal oxide second electrode interface layer is within about 10% of an associated lattice parameter of the dielectric layer.

### Claim 16 (depends on 14)

The semiconductor layer stack of claim 14 wherein the first electrode layer comprises one of a metal, a metal alloy, a conductive metal oxide, a conductive metal silicide, a conductive metal carbide, a conductive metal nitride, or combinations thereof.

### Claim 17 (depends on 16)

The semiconductor layer stack of claim 16 wherein the first electrode layer comprises one of molybdenum oxide, tungsten oxide, ruthenium oxide, iridium oxide, chromium oxide, manganese oxide, tin oxide, or cobalt oxide.

### Claim 18 (depends on 17)

The semiconductor layer stack of claim 17 wherein the first electrode layer comprises molybdenum oxide.

### Claim 19 (depends on 14)

The semiconductor layer stack of claim 14 wherein the dielectric layer comprises a dopant.

### Claim 20 (depends on 19)

The semiconductor layer stack of claim 19 wherein the dielectric material comprises TiO2 and wherein the dopant comprises one of Al, Ce, Co, Er, Ga, Gd, Ge, Hf, In, La, Lu, Mg, Mn, Nd, Pr, Sc, Si, Sn, Sr, Y, Zr, or combinations thereof.

### Claim 21 (depends on 14)

The semiconductor layer stack of claim 14 wherein the metal oxide second electrode interface layer comprises one of molybdenum oxide, tungsten oxide, ruthenium oxide, iridium oxide, chromium oxide, manganese oxide, tin oxide, or cobalt oxide.