# US 8,541,863 B2 · Data retention in a single poly EPROM cell

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- Number: US 8,541,863 B2
- Document ID: US8541863B2
- Status: Granted
- Kind: B2
- Application number: 12/955,061
- Filed: 2010-11-29
- Published: 2012-05-31
- Granted: 2013-09-24
- Earliest claimed: 2010-11-29
- Assignees: National Semiconductor Corporation
- Applicants: Venkat Raghavan; Andrew Strachan
- Inventors: Venkat Raghavan; Andrew Strachan
- Web page: https://patentgrep.com/patent/US8541863B2

## CPC

- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10B 41/60: the control gate being a doped region, e.g. single-poly memory cell
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

An electrically programmable read only memory (EPROM) BIT cell structure formed on a semiconductor substrate comprises an N-type epitaxial layer formed on the semiconductor substrate, an N-type well region formed in the epitaxial layer, LOCOS field oxide formed at the periphery of the well region to define an active device region in the well region, a field oxide ring formed in the active region and space-apart from the LOCOS field oxide to define an EPROM BIT cell region, and an EPROM BIT cell formed in the EPROM BIT cell region.

## Claims

### Claim 1

A single poly electrically programmable read only memory (EPROM) cell with improved data retention comprising:
A P-type substrate, having top and bottom surfaces;
an N-type buried layer formed in the top surface of the P-type substrate;
an N-type epitaxial layer formed on the top surface of the P-type substrate and the N-type buried layer;
an N-type well region formed in the N-type epitaxial layer;
a LOCOS field oxide isolation formed at the periphery of the well region, extending outwardly from the N-type well region to the next device isolation, thereby defining the boundary of the N-type well region;
a field oxide stress relief ring formed in the N-type well region, extending inwardly and spaced-apart from the LOCOS field oxide isolation to define an EPROM BIT cell region in the N-type well region, wherein no contacts, additional diodes or guard rings exist between the field oxide stress relief ring and the LOCOS field oxide;
an EPROM BIT cell configured as a PMOS transistor, having a floating gate formed in the upper surface of the N-type well, contained within the field oxide stress relief ring;
wherein the EPROM BIT cell comprises:
a P+ source region formed within the field oxide stress relief ring;
a P+ drain region formed within the field oxide stress relief ring and spaced-apart from the source region to define a N-type channel region therebetween;
wherein the source region is spaced-apart from the field oxide stress relief ring, and further comprising an N-type contact region formed between the source region and the field oxide stress relief ring; and
a conductive gate comprised of N-doped polysilicon formed over the channel region and separated therefrom by intervening dielectric material.

### Claim 2 (depends on 1)

The EPROM cell structure of claim 1, wherein the field oxide stress relief ring is spaced-apart from the LOCOS field oxide isolation by greater than or equal to 1.5 μm.