# US 8,541,862 B2 · Semiconductor device with self-biased isolation

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- Number: US 8,541,862 B2
- Document ID: US8541862B2
- Status: Granted
- Kind: B2
- Application number: 13/307,449
- Filed: 2011-11-30
- Published: 2013-05-30
- Granted: 2013-09-24
- Earliest claimed: 2011-11-30
- Assignees: Freescale Semiconductor, Inc.
- Applicants: Hongning Yang; Jiang-Kai Zuo
- Inventors: Hongning Yang; Jiang-Kai Zuo
- Web page: https://patentgrep.com/patent/US8541862B2

## CPC

- H10D 62/109: {Reduced surface field [RESURF] PN junction structures}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 64/27: Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10W 10/031: {of isolation regions comprising PN junctions}
- H10W 10/30: Isolation regions comprising PN junctions
- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A device includes a semiconductor substrate including a surface, a drain region in the semiconductor substrate having a first conductivity type, a well region in the semiconductor substrate on which the drain region is disposed, the well region having the first conductivity type, a buried isolation layer in the semiconductor substrate extending across the well region, the buried isolation layer having the first conductivity type, a reduced surface field (RESURF) region disposed between the well region and the buried isolation layer, the RESURF region having a second conductivity type, and a plug region in the semiconductor substrate extending from the surface of the substrate to the RESURF region, the plug region having the second conductivity type.

## Claims

### Claim 1

A device comprising:
a semiconductor substrate comprising a surface;
a drain region in the semiconductor substrate having a first conductivity type;
a well region in the semiconductor substrate on which the drain region is disposed, the well region having the first conductivity type;
a buried isolation layer in the semiconductor substrate extending across the well region, the buried isolation layer having the first conductivity type;
a reduced surface field (RESURF) region disposed between the well region and the buried isolation layer, the RESURF region having a second conductivity type; and
a plug region in the semiconductor substrate extending from the surface of the substrate to the RESURF region, the plug region having the second conductivity type.

### Claim 2 (depends on 1)

The device of claim 1, further comprising a device isolation well in the semiconductor substrate, wherein:
the device isolation well has the first conductivity type;
the buried isolation layer is coupled to the device isolation well; and
the device isolation well is electrically tied to the plug region.

### Claim 3 (depends on 1)

The device of claim 1, wherein the plug region comprises a plurality of plugs spaced from one another by respective portions of the drain region.

### Claim 4 (depends on 3)

The device of claim 3, wherein each plug is sized and spaced from one or more adjacent plugs of the plurality of plugs to bias the plug region at a voltage that falls in a range from about 50% to about 80% of a voltage applied to the drain region.

### Claim 5 (depends on 1)

The device of claim 1, wherein the plug region electrically links an upper surface of the substrate to an upper surface of the RESURF region.

### Claim 6 (depends on 1)

The device of claim 1, wherein the well region is positioned in the semiconductor substrate as a drift region.

### Claim 7 (depends on 1)

The device of claim 1, further comprising a body region in the semiconductor substrate and a source region disposed on the body region, wherein the body region has the second conductivity type and is spaced from the well region and the RESURF region.

### Claim 8 (depends on 1)

The device of claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.

### Claim 9 (depends on 1)

The device of claim 1, wherein the semiconductor substrate comprises an epitaxial layer, and wherein the buried isolation layer is disposed in the epitaxial layer.

### Claim 10

An electronic apparatus comprising:
a reduced surface field (RESURF) transistor comprising:
a first semiconductor region having a first conductivity type;
a second semiconductor region having a second conductivity type and disposed above the first semiconductor region;
a third semiconductor region having the first conductivity type and disposed above the second semiconductor region;
a fourth semiconductor region having the first conductivity type and disposed above the third semiconductor region; and
a fifth semiconductor region having the second conductivity type, wherein the fifth semiconductor region extends through the third semiconductor region to reach the second semiconductor region, and is electrically tied to the first semiconductor region, to bias the first semiconductor region based on a voltage applied to the fourth semiconductor region.

### Claim 11 (depends on 10)

The electronic apparatus of claim 10, further comprising a device isolation well surrounding the RESURF transistor, wherein:
the device isolation well has the first conductivity type;
the first semiconductor region is coupled to the device isolation well; and
the first and fifth semiconductor regions are electrically tied via the device isolation well.

### Claim 12 (depends on 10)

The electronic apparatus of claim 10, wherein the fifth semiconductor region comprises a plurality of plugs spaced from one another by respective portions of the fourth semiconductor region.

### Claim 13 (depends on 12)

The electronic apparatus of claim 12, wherein each plug is sized and spaced from one or more adjacent plugs of the plurality of plugs to bias the first semiconductor region at a reduced voltage that falls in a range from about 50% to about 80% of the voltage applied to the fourth semiconductor region.

### Claim 14 (depends on 10)

The electronic apparatus of claim 10, wherein the first semiconductor region and an upper surface of the second semiconductor region are electrically linked via the fifth semiconductor region.

### Claim 15 (depends on 10)

The electronic apparatus of claim 10, wherein:
the first semiconductor region is configured as a barrier layer,
the third semiconductor region is positioned within the RESURF transistor as a drift region,
the fourth semiconductor region is configured as a drain region, and
the fifth semiconductor region is configured as a plug region.

### Claim 16 (depends on 10)

The electronic apparatus of claim 10, wherein the first conductivity type is n-type and the second conductivity type is p-type.