# US 8,541,847 B2 · Semiconductor device and method for fabricating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,541,847 B2 - Document ID: US8541847B2 - Status: Granted - Kind: B2 - Application number: 13/201,618 - Filed: 2010-09-25 - Published: 2012-07-26 - Granted: 2013-09-24 - Earliest claimed: 2010-03-15 - Assignees: Peking University - Applicants: Xia An; Yue Guo; Quanxin Yun; Ru Huang; Xing Zhang - Inventors: Xia An; Yue Guo; Quanxin Yun; Ru Huang; Xing Zhang - Web page: https://patentgrep.com/patent/US8541847B2 ## CPC - H10P 30/204: {into Group IV semiconductors} - H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET} - H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)} - H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain} - H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge - H10P 30/208: {of electrically inactive species} - H10P 30/21: {of electrically active species} - H10P 30/28: characterised by an annealing step, e.g. for activation of dopants - H10D 84/0167: {Manufacturing their channels} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract The present invention provides a semiconductor device and a method for fabricating the same, wherein the method comprises: providing a germanium-based semiconductor substrate having a plurality of active regions and device isolation regions between the plurality of the active regions, wherein a gate dielectric layer and a gate over the gate dielectric layer are provided on the active regions, and the active regions include source and drain extension regions and deep source and drain regions; performing a first ion implantation process with respect to the source and drain extension regions, wherein the ions implanted in the first ion implantation process include silicon or carbon; performing a second ion implantation process with respect to the source and drain extension regions; performing a third ion implantation process with respect to the deep source and drain regions; performing an annealing process with respect to the germanium-based semiconductor substrate which has been subjected to the third ion implantation process. According to the method for fabricating a semiconductor device, through the implantation of silicon impurities, appropriate stress may be introduced into the germanium channel effectively by the mismatch of lattices in the source and drain regions, so that the mobility of electrons in the channel is enhanced and the performance of the device is improved. ## Claims ### Claim 1 A method for fabricating a semiconductor device, characterized in that the method comprises steps of: providing a germanium-based semiconductor substrate having a plurality of active regions and device isolation regions between the plurality of the active regions, wherein a gate dielectric layer and a gate over the gate dielectric layer are provided on the active regions, and the active regions include source and drain extension regions and deep source and drain regions; performing a first ion implantation process with respect to the source and drain extension regions, wherein ions implanted during the first ion implantation process include silicon or carbon; performing a second ion implantation process with respect to the source and drain extension regions; performing a third ion implantation process with respect to the deep source and drain regions; performing an annealing process with respect to the germanium-based semiconductor substrate which has been subjected to the third ion implantation process. ### Claim 2 (depends on 1) The method for fabricating a semiconductor device according to claim 1, characterized in that, the germanium-based semiconductor substrate is of P-type, and N-type impurities are implanted during the second ion implantation process and/or the third ion implantation process. ### Claim 3 (depends on 2) The method for fabricating a semiconductor device according to claim 2, characterized in that, the germanium-based semiconductor substrate includes a bulk germanium substrate, a germanium-on-insulator substrate or a silicon-based epitaxial germanium substrate. ### Claim 4 (depends on 2) The method for fabricating a semiconductor device according to claim 2, characterized in that, the N-type impurities include one or more selected form P, As and Sb. ### Claim 5 (depends on 1) The method for fabricating a semiconductor device according to claim 1, characterized in that, the annealing process includes rapid thermal annealing, laser annealing or flash annealing. ### Claim 6 (depends on 1) The method for fabricating a semiconductor device according to claim 1, characterized in that, the doping dosage of the first ion implantation process is 1e13 to 1e16 atom/cm2. ### Claim 7 (depends on 1) The method for fabricating a semiconductor device according to claim 1, characterized in that, the doping dosage of the third ion implantation process is 5e14 to 1e16 atom/cm2. ### Claim 8 (depends on 1) The method for fabricating a semiconductor device according to claim 1, characterized in that, a uniaxial tensile stress in a direction parallel to a germanium channel and a compressive stress in a direction perpendicular to a channel plane are introduced into the germanium channel after performing the implantation of silicon or carbon to the source and drain extension regions. ### Claim 9 (depends on 1) The method for fabricating a semiconductor device according to claim 1, characterized in that the method further comprises: forming sidewalls on both sides of the gate, before the step of performing the annealing process with respect to the germanium-based semiconductor substrate which has been subjected to the third ion implantation process. ### Claim 10 (depends on 2) The method for fabricating a semiconductor device according to claim 2, characterized in that, the doping dosage of the third ion implantation process is 5×e14 to 1×e16 atom/cm2. ### Claim 11 A semiconductor device comprising: a germanium-based semiconductor substrate, a plurality of active regions in the germanium based semiconductor substrate and device isolation regions between the plurality of the active regions, and a gate dielectric layer on the active regions and a gate on the gate dielectric layer, wherein the active regions include source and drain extension regions and deep source and drain regions; characterized in that: silicon or carbon impurities are contained in the source and drain extension regions; and the silicon or carbon impurities are doped into the source and drain extension regions by performing a first ion implantation process with respect to the source and drain extension regions.