# US 8,541,846 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,541,846 B2 - Document ID: US8541846B2 - Status: Granted - Kind: B2 - Application number: 13/026,525 - Filed: 2011-02-14 - Published: 2011-08-25 - Granted: 2013-09-24 - Earliest claimed: 2010-02-19 - Assignees: Semiconductor Energy Laboratory Co., Ltd. - Applicants: Toshihiko Saito - Inventors: Toshihiko Saito - Web page: https://patentgrep.com/patent/US8541846B2 ## CPC - H10D 86/60: wherein the TFTs are in active matrices - H10B 41/35: with a cell select transistor, e.g. NAND - H10B 99/00: Subject matter not provided for in other groups of this subclass - H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs} - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 30/68: Floating-gate IGFETs - H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate} - H10D 62/115: {Dielectric isolations, e.g. air gaps} - H10D 62/402: {Amorphous materials} - H10D 62/80: characterised by the materials - H10D 84/83: of only insulated-gate FETs [IGFET] - H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO} - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 86/471: {having different architectures, e.g. having both top-gate and bottom-gate TFTs} - H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10B: ELECTRONIC MEMORY DEVICES ## Abstract At least one of a plurality of transistors which are highly integrated in an element is provided with a back gate without increasing the number of manufacturing steps. In an element including a plurality of transistors which are longitudinally stacked, at least a transistor in an upper portion includes a metal oxide having semiconductor characteristics, a same layer as a gate electrode of a transistor in a lower portion is provided to overlap with a channel formation region of the transistor in an upper portion, and part of the same layer as the gate electrode functions as a back gate of the transistor in an upper portion. The transistor in a lower portion which is covered with an insulating layer is subjected to planarization treatment, whereby the gate electrode is exposed and connected to a layer functioning as source and drain electrodes of the transistor in an upper portion. ## Claims ### Claim 1 A semiconductor device comprising an element, the element comprising: a first transistor comprising a first semiconductor layer and a first gate electrode; an insulating layer over at least a part of the first transistor; and a second transistor comprising a back gate electrode, a second semiconductor layer over the back gate electrode and a second gate electrode over the second semiconductor layer, wherein the insulating layer is interposed between the second semiconductor layer and the back gate electrode, wherein the second semiconductor layer comprises an oxide semiconductor film, and wherein the back gate electrode is formed from a same film as the first gate electrode. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the first transistor is supported by an SOI substrate. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the first transistor is supported by a silicon substrate. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the insulating layer has a leveled upper surface. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein a top surface of the first gate electrode is not covered by the insulating layer. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein a distance between the back gate electrode and a channel formation region of the second semiconductor layer is equal to a thickness of the first semiconductor layer. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein the element is a memory element. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein the element is an inversion element. ### Claim 9 A semiconductor device comprising an element, the element comprising: a first transistor comprising a first semiconductor layer and a first gate electrode; an insulating layer over at least a part of the first transistor; and a second transistor comprising a back gate electrode, a second semiconductor layer over the back gate electrode, a second gate electrode over the second semiconductor layer and a source electrode and a drain electrode, wherein the insulating layer is interposed between the second semiconductor layer and the back gate electrode, wherein the second semiconductor layer comprises an oxide semiconductor film, wherein the back gate electrode is formed from a same film as the first gate electrode, and wherein the first gate electrode is in contact with one of the source electrode and the drain electrode. ### Claim 10 (depends on 9) The semiconductor device according to claim 9, wherein the first transistor is supported by an SOI substrate. ### Claim 11 (depends on 9) The semiconductor device according to claim 9, wherein the first transistor is supported by a silicon substrate. ### Claim 12 (depends on 9) The semiconductor device according to claim 9, wherein the insulating layer has a leveled upper surface. ### Claim 13 (depends on 9) The semiconductor device according to claim 9, wherein a top surface of the first gate electrode is not covered by the insulating layer. ### Claim 14 (depends on 9) The semiconductor device according to claim 9, wherein a distance between the back gate electrode and a channel formation region of the second semiconductor layer is equal to a thickness of the first semiconductor layer. ### Claim 15 (depends on 9) The semiconductor device according to claim 9, wherein the element is a memory element. ### Claim 16 (depends on 9) The semiconductor device according to claim 9, wherein the element is an inversion element. ### Claim 17 A semiconductor device comprising an element, the element comprising: a first transistor comprising a first semiconductor layer and a first gate electrode; an insulating layer over at least a part of the first transistor; a second transistor comprising a back gate electrode, a second semiconductor layer over the back gate electrode and a second gate electrode over the second semiconductor layer; and a capacitor comprising a first capacitor electrode and a second capacitor electrode over the first capacitor electrode, wherein the insulating layer is interposed between the second semiconductor layer and the back gate electrode, wherein the second semiconductor layer comprises an oxide semiconductor film, and wherein the back gate electrode, the first gate electrode and the second capacitor electrode are formed from a same film as the first gate electrode. ### Claim 18 (depends on 17) The semiconductor device according to claim 17, wherein the first transistor is supported by an SOI substrate. ### Claim 19 (depends on 17) The semiconductor device according to claim 17, wherein the first transistor is supported by a silicon substrate. ### Claim 20 (depends on 17) The semiconductor device according to claim 17, wherein the insulating layer has a leveled upper surface. ### Claim 21 (depends on 17) The semiconductor device according to claim 17, wherein a top surface of the first gate electrode is not covered by the insulating layer. ### Claim 22 (depends on 17) The semiconductor device according to claim 17, wherein a distance between the back gate electrode and a channel formation region of the second semiconductor layer is equal to a thickness of the first semiconductor layer. ### Claim 23 (depends on 17) The semiconductor device according to claim 17, wherein the element is a memory element. ### Claim 24 (depends on 17) The semiconductor device according to claim 17, wherein the element is an inversion element.