# US 8,541,843 B2 · Nonvolatile nanotube programmable logic devices and a nonvolatile nanotube field programmable gate array using same

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- Number: US 8,541,843 B2
- Document ID: US8541843B2
- Status: Granted
- Kind: B2
- Application number: 12/536,803
- Filed: 2009-08-06
- Published: 2010-04-01
- Granted: 2013-09-24
- Earliest claimed: 2008-08-14
- Assignees: Nantero, Inc.
- Applicants: Claude L. Bertin; Rinn Cleavelin; Thomas Rueckes
- Inventors: Claude L. Bertin; Rinn Cleavelin; Thomas Rueckes
- Web page: https://patentgrep.com/patent/US8541843B2

## CPC

- G11C 13/0069: {Writing or programming circuits or methods}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0061: {Timing circuits or methods}
- G11C 13/025: {using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes}
- G11C 23/00: Digital stores characterised by movement of mechanical parts to effect storage, e.g. using balls; Storage elements therefor
- G11C 29/02: Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C 29/021: {in voltage or current generators}
- G11C 29/023: {in clock generator or timing circuitry}
- G11C 29/028: {with adaption or trimming of parameters}
- H03K 19/17728: Reconfigurable logic blocks, e.g. lookup tables
- H03K 19/17736: Structural details of routing resources
- H03K 19/1776: for memories
- H03K 19/1778: Structural details for adapting physical parameters
- H03K 19/17796: for physical disposition of blocks
- G11C 2013/0042: {Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB]}
- G11C 2013/0054: {Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell}
- G11C 2213/35: Material including carbon, e.g. graphite, grapheme
- G11C 2213/82: Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials
- Y10S 977/94: in a logic circuit
- G11C: STATIC STORES (semiconductor memory devices H10B)
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate.

## Claims

### Claim 1

An integrated nanotube device comprising:
an insulating substrate;
at least one field effect transistor on the insulating substrate, the at least one field effect transistor comprising:
a patterned nanotube fabric, being substantially free of metallic nanotubes and having a plurality of semiconducting nanotubes, the patterned nanotube fabric having a source region and a drain region, wherein the source region and drain region are in a spaced relation relative to one another and wherein the spaced relation defines a channel region in the patterned nanotube fabric;
a gate element electrically coupled to the channel region, wherein the gate element modulates the conductivity of the channel region such that a conductive pathway is formed or unformed between the source and drain in response to electrical stimulus;
wherein the at least one field effect transistor is a p-type field effect transistor; and
wherein the at least one field effect transistor has the gate element embedded in the insulating substrate.

### Claim 2 (depends on 1)

The integrated nanotube device of claim 1, wherein the at least one field effect transistor has a gate insulator is formed above the gate element and wherein the patterned nanotube fabric is formed above the gate insulator.

### Claim 3 (depends on 1)

The integrated nanotube device of claim 1, further comprising a first contact embedded in the insulating substrate.

### Claim 4 (depends on 3)

The integrated nanotube device of claim 3, further comprising a second contact embedded in the insulating substrate.

### Claim 5

An integrated nanotube device comprising:
an insulating substrate;
at least one field effect transistor on the insulating substrate, the at least one field effect transistor comprising:
a patterned nanotube fabric, being substantially free of metallic nanotubes and having a plurality of semiconducting nanotubes, the patterned nanotube fabric having a source region and a drain region, wherein the source region and drain region are in a spaced relation relative to one another and wherein the spaced relation defines a channel region in the patterned nanotube fabric;
a gate element electrically coupled to the channel region, wherein the gate element modulates the conductivity of the channel region such that a conductive pathway is formed or unformed between the source and drain in response to electrical stimulus;
wherein the at least one field effect transistor is an n-type field effect transistor; and
wherein the at least one field effect transistor has the gate element embedded in the insulating substrate.

### Claim 6 (depends on 5)

The integrated nanotube device of claim 5, wherein the at least one field effect transistor has a gate insulator is formed above the gate element and wherein the patterned nanotube fabric is formed above the gate insulator.

### Claim 7 (depends on 5)

The integrated nanotube device of claim 5, further comprising a first contact embedded in the insulating substrate.

### Claim 8 (depends on 7)

The integrated nanotube device of claim 7, further comprising a second contact embedded in the insulating substrate.

### Claim 9

An integrated nanotube device comprising:
an insulating substrate;
a patterned nanotube fabric, being substantially free of metallic nanotubes, comprising semiconducting nanotubes, wherein the patterned nanotube fabric has a drain region between and in a spaced relation with a first and second source regions and wherein the spaced relation with the first and second source regions defines a first and second channel regions;
a first gate electrically coupled to the first channel region, the first gate modulating the conductivity of the first channel region to form or unform an electrically conductive pathway between the first source region and the drain region in response to a first electrical stimulus;
a second gate electrically coupled to the second channel region, the second gate modulating the conductivity of the second channel region to form or unform an electrically conductive pathway between the first source region and the drain region in response to a second electrical stimulus.

### Claim 10 (depends on 9)

The integrated nanotube device of claim 9, wherein the nanotube fabric and the first and second gate regions form a pair of complementary n-type an p-type nanotube field effect transistors.